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563e230a6a
- rtl/bplib
- arty/migui_arty_gsim.vhd: cosmetics
- nexys4d/mig_a.prj: BUGFIX: SysResetPolarity ACTIVE HIGH; InputClk 100 MHz
- nexys4d/migui_nexys4d_gsim.vhd: cosmetics
- rtl/sys_gen
- tst_mig/nexys4d/sys_tst_mig_n4d: use 100 MHz MIG SYS_CLK; add clock monitor
- tst_sram/nexys4d/sys_tst_sram_n4d: use 100 MHz MIG SYS_CLK
- w11a/nexys4d/sys_w11a_n4d: use 100 MHz MIG SYS_CLK
- */nexys4*/tb/tbrun.yml: drop n4 from, add n4d to default
- tools/exptest/sys
- sys_w11a_arty_setup.tcl: add missing memsize definition
- sys_w11a_{br_arty,br_n4d,n4d}_setup.tcl: added
16 lines
490 B
Tcl
16 lines
490 B
Tcl
# $Id: sys_w11a_br_n4d_setup.tcl 1201 2019-08-10 16:51:22Z mueller $
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# SPDX-License-Identifier: GPL-3.0-or-later
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# Copyright 2019- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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#
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# Revision History:
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# Date Rev Version Comment
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# 2019-08-08 1201 1.0 Initial version
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#---
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# setup for sys_w11a_br_n4d
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#
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set ::genv(rri_opt) "-tuD,12M,break,cts"
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set ::genv(sys_path) "rtl/sys_gen/w11a/nexys4d_bram"
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set ::genv(memsize) 512
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source ostest_midmem_setup.tcl
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source mcode_setup.tcl
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