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22bb8e011c
- sfs_gsim_core: new common simulation core
- {dcm,s6_cmt,s7_cmt}_sfs_gsim: use now sfs_gsim_core
- s7_cmt_sfs_tb: removed, use now sfs_gsim_core
- rtl/bplib/*/tb/tb_*: use now sfs_gsim_core
- tst_serloop/nexys*/tb/tb_tst_serloop*_n*: use now sfs_gsim_core
66 lines
2.2 KiB
VHDL
66 lines
2.2 KiB
VHDL
-- $Id: dcm_sfs_gsim.vhd 1065 2018-11-04 11:32:06Z mueller $
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--
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-- Copyright 2010-2018 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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-- This program is free software; you may redistribute and/or modify it under
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-- the terms of the GNU General Public License as published by the Free
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-- Software Foundation, either version 3, or (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful, but
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-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
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-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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-- for complete details.
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--
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------------------------------------------------------------------------------
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-- Module Name: dcm_sfs - sim
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-- Description: DCM for simple frequency synthesis
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-- simple vhdl model, without Xilinx UNISIM primitives
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--
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-- Dependencies: -
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-- Test bench: -
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-- Target Devices: generic Spartan-3A,-3E
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-- Tool versions: xst 12.1-14.7; ghdl 0.29-0.34
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--
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-- Revision History:
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-- Date Rev Version Comment
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-- 2018-11-03 1065 1.1 use sfs_gsim_core
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-- 2011-11-17 426 1.0.1 rename dcm_sp_sfs -> dcm_sfs
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-- 2010-11-12 338 1.0 Initial version
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use work.slvtypes.all;
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use work.xlib.all;
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entity dcm_sfs is -- DCM for simple frequency synthesis
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generic (
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CLKFX_DIVIDE : positive := 1; -- FX clock divide (1-32)
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CLKFX_MULTIPLY : positive := 1; -- FX clock multiply (2-32) (1->no DCM)
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CLKIN_PERIOD : real := 20.0); -- CLKIN period (def is 20.0 ns)
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port (
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CLKIN : in slbit; -- clock input
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CLKFX : out slbit; -- clock output (synthesized freq.)
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LOCKED : out slbit -- dcm locked
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);
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end dcm_sfs;
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architecture sim of dcm_sfs is
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begin
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-- generate clock
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SFS: sfs_gsim_core
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generic map (
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VCO_DIVIDE => 1,
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VCO_MULTIPLY => CLKFX_MULTIPLY,
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OUT_DIVIDE => CLKFX_DIVIDE)
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port map (
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CLKIN => CLKIN,
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CLKFX => CLKFX,
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LOCKED => LOCKED
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);
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end sim;
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