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70 lines
2.0 KiB
VHDL
70 lines
2.0 KiB
VHDL
-- $Id: usr_access_unisim.vhd 984 2018-01-02 20:56:27Z mueller $
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--
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-- Copyright 2016- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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-- This program is free software; you may redistribute and/or modify it under
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-- the terms of the GNU General Public License as published by the Free
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-- Software Foundation, either version 3, or (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful, but
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-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
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-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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-- for complete details.
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--
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------------------------------------------------------------------------------
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-- Module Name: usr_access_unisim - syn
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-- Description: Wrapper for USR_ACCESS* entities
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--
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-- Dependencies: -
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-- Test bench: -
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-- Target Devices: generic Series-7
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-- Tool versions: viv 2015.4; ghdl 0.33
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--
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-- Revision History:
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-- Date Rev Version Comment
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-- 2016-04-02 758 1.0 Initial version
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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library unisim;
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use unisim.vcomponents.ALL;
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use work.slvtypes.all;
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entity usr_access_unisim is -- wrapper for USR_ACCESS family
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port (
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DATA : out slv32 -- usr_access register value
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);
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end usr_access_unisim;
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architecture syn of usr_access_unisim is
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signal DATA_RAW : slv32 := (others=>'0');
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begin
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UA : USR_ACCESSE2
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port map (
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CFGCLK => open,
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DATA => DATA_RAW,
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DATAVALID => open
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);
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-- the USR_ACCESSE2 simulation model unfortunately returns always 'UUUU'
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-- no way to configure it for reasonable simulation behavior
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-- there this sanitiser
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proc_data: process (DATA_RAW)
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variable idata : slv32 := (others=>'0');
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begin
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idata := to_x01(DATA_RAW);
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if is_x(idata) then
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idata := (others=>'0');
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end if;
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DATA <= idata;
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end process proc_data;
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end syn;
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