mirror of
https://github.com/wfjm/w11.git
synced 2026-05-05 23:55:01 +00:00
9b7b3bd5c8
- ibus/ib_rlim_gen: add CPUSUSP port; RLIM_CEV now slv8
- ibus/ib_rlim_slv: RLIM_CEV now slv8
- ibus/ibdr_{dl11,lp11_buf}: RLIM_CEV now slv8
- bin/asm-11: fix -help text
- bin/ldadump: added, lda file dumper
- src
- Rw11Cntl: add UnitSetup(), UnitSetupAll()
- Rw11Cntl{DEUNA,DL11,RHRP,RK11,RL11,TM11}: call UnitSetupAll() in Start()
- Rw11CntlLP11: remove SetOnline(), use UnitSetup()
- Rw11CntlPC11:
- BootCode(): boot loader rewritten
- remove SetOnline(), use UnitSetup()
- Rw11Cpu
- add defs for w11 cpu component addresses;
- add MemSize(),MemWriteByte()
- LoadAbs(): return start, better odd byte handling;
- Rw11VirtStream: add Error(),Eof()
- RtclRw11Cpu:
- BUGFIX: M_wtcpu(): check cpu attn in no-server case
- add MemSize() getter
- M_loadabs(): add -trace and start
- ibd_pc11/util.tcl: use rdy instead of done in PCSR
- rw11/util.tcl: setup_lp: add rlim option
137 lines
4.1 KiB
VHDL
137 lines
4.1 KiB
VHDL
-- $Id: ib_rlim_slv.vhd 1131 2019-04-14 13:24:25Z mueller $
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--
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-- Copyright 2019- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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-- This program is free software; you may redistribute and/or modify it under
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-- the terms of the GNU General Public License as published by the Free
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-- Software Foundation, either version 3, or (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful, but
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-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
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-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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-- for complete details.
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--
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------------------------------------------------------------------------------
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-- Module Name: ib_rlim_slv - syn
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-- Description: ibus rate limter - slave
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--
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-- Dependencies: -
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-- Test bench: -
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-- Target Devices: generic
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-- Tool versions: ise 14.7; viv 2017.2; ghdl 0.35
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--
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-- Revision History:
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-- Date Rev Version Comment
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-- 2019-04-14 1131 1.1 RLIM_CEV now slv8
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-- 2019-03-17 1123 1.0 Initial version
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-- 2019-03-15 1122 0.1 First draft
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--
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-- Notes:
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-- sel ce-scale rate in slv
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-- 0 - 8 cycles
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-- 1 1: 1 8 usec 125.0 kHz
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-- 2 1: 2 16 usec 62.5 kHz
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-- 3 1: 4 32 usec 31.2 kHz
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-- 4 1: 8 64 usec 15.6 kHz
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-- 5 1: 16 256 usec 3.9 kHz
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-- 6 1: 32 512 usec 2.0 kHz
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-- 7 1: 64 1024 usec 1.0 kHz
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.slvtypes.all;
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-- ----------------------------------------------------------------------------
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entity ib_rlim_slv is -- ibus rate limter - slave
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port (
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CLK : in slbit; -- clock
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RESET : in slbit; -- system reset
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RLIM_CEV : in slv8; -- clock enable vector
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SEL : in slv3; -- rlim select
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START : in slbit; -- start timer
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STOP : in slbit; -- stop timer
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DONE : out slbit; -- 1 cycle pulse when expired
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BUSY : out slbit -- timer running
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);
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end ib_rlim_slv;
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architecture syn of ib_rlim_slv is
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type regs_type is record -- state registers
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cnt : slv3; -- counter
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busy : slbit; -- busy
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end record regs_type;
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constant regs_init : regs_type := (
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(others=>'0'), -- cnt
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'0' -- busy
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);
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signal R_REGS : regs_type := regs_init;
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signal N_REGS : regs_type := regs_init;
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begin
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proc_regs: process (CLK)
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begin
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if rising_edge(CLK) then
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if RESET = '1' then
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R_REGS <= regs_init;
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else
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R_REGS <= N_REGS;
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end if;
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end if;
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end process proc_regs;
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proc_next : process (R_REGS, RLIM_CEV, SEL, START, STOP)
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variable r : regs_type := regs_init;
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variable n : regs_type := regs_init;
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variable idone : slbit := '0';
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variable ice : slbit := '0';
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begin
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r := R_REGS;
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n := R_REGS;
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ice := '0';
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case SEL is
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when "000" => ice := RLIM_CEV(0); -- every cycle
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when "001" => ice := RLIM_CEV(1); -- every CE_USEC
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when "010" => ice := RLIM_CEV(2); -- every 2nd CE_USEC
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when "011" => ice := RLIM_CEV(3); -- every 4th CE_USEC
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when "100" => ice := RLIM_CEV(4); -- every 8th CE_USEC
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when "101" => ice := RLIM_CEV(5); -- every 32nd CE_USEC
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when "110" => ice := RLIM_CEV(6); -- every 64th CE_USEC
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when "111" => ice := RLIM_CEV(7); -- every 128th CE_USEC
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when others => null;
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end case;
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idone := '0';
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if STOP = '1' then
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n.busy := '0';
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idone := r.busy;
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elsif START = '1' then
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n.busy := '1';
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n.cnt := "000";
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elsif r.busy = '1' then
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if ice = '1' then
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n.cnt := slv(unsigned(r.cnt) + 1);
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if r.cnt = "111" then
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n.busy := '0';
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idone := '1';
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end if;
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end if;
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end if;
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N_REGS <= n;
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DONE <= idone;
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BUSY <= r.busy;
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end process proc_next;
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end syn;
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