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f6775f7d05
- added xon/xoff (software flow control) support to serport library - added test systems for serport verification - use new serport stack in sys_w11a_* and sys_tst_rlink_* systems
113 lines
3.1 KiB
VHDL
113 lines
3.1 KiB
VHDL
-- $Id: gray_cnt_n.vhd 418 2011-10-23 20:11:40Z mueller $
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--
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-- Copyright 2007- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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-- This program is free software; you may redistribute and/or modify it under
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-- the terms of the GNU General Public License as published by the Free
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-- Software Foundation, either version 2, or at your option any later version.
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--
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-- This program is distributed in the hope that it will be useful, but
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-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
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-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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-- for complete details.
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--
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------------------------------------------------------------------------------
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-- Module Name: gray_cnt_n - syn
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-- Description: Genric width Gray code counter
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--
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-- Dependencies: -
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-- Test bench: tb/tb_debounce_gen
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-- Target Devices: generic
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-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25
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-- Revision History:
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-- Date Rev Version Comment
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-- 2007-12-26 106 1.0 Initial version
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--
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-- Some synthesis results:
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-- - 2007-12-27 ise 8.2.03 for xc3s1000-ft256-4:
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-- DWIDTH LUT Flop clock(xst est.)
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-- 4 6 5 305MHz/ 3.28ns
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-- 5 8 6 286MHz/ 2.85ns
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-- 8 13 9 234MHz/ 4.26ns
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-- 16 56 17 149MHz/ 6.67ns
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-- 32 95 33 161MHz/ 6.19ns
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-- 64 188 68 126MHz/ 7.90ns
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use work.slvtypes.all;
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use work.genlib.all;
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entity gray_cnt_n is -- n bit gray code counter
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generic (
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DWIDTH : positive := 8); -- data width
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port (
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CLK : in slbit; -- clock
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RESET : in slbit := '0'; -- reset
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CE : in slbit := '1'; -- count enable
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DATA : out slv(DWIDTH-1 downto 0) -- data out
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);
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end entity gray_cnt_n;
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architecture syn of gray_cnt_n is
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signal R_AUX : slbit := '1';
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signal R_DATA : slv(DWIDTH-1 downto 0) := (others=>'0');
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signal N_DATA : slv(DWIDTH-1 downto 0) := (others=>'0');
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begin
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assert DWIDTH>=3
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report "assert(DWIDTH>=3): only 3 bit or larger supported"
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severity failure;
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proc_regs: process (CLK)
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begin
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if rising_edge(CLK) then
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if RESET = '1' then
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R_AUX <= '1';
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R_DATA <= (others=>'0');
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elsif CE = '1' then
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R_AUX <= not R_AUX;
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R_DATA <= N_DATA;
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end if;
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end if;
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end process proc_regs;
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proc_next: process (R_AUX, R_DATA)
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variable r : slv(DWIDTH-1 downto 0) := (others=>'0');
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variable n : slv(DWIDTH-1 downto 0) := (others=>'0');
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variable s : slbit := '0';
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begin
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r := R_DATA;
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n := R_DATA;
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s := '1';
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if R_AUX = '1' then
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n(0) := not r(0);
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else
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for i in 1 to DWIDTH-2 loop
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if s='1' and r(i-1)='1' then
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n(i) := not r(i);
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end if;
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s := s and not r(i-1);
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end loop;
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if s = '1' then
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n(DWIDTH-1) := r(DWIDTH-2);
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end if;
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end if;
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N_DATA <= n;
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end process proc_next;
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DATA <= R_DATA;
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end syn;
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