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105 lines
3.0 KiB
VHDL
105 lines
3.0 KiB
VHDL
-- $Id: sfs_gsim_core.vhd 1181 2019-07-08 17:00:50Z mueller $
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-- SPDX-License-Identifier: GPL-3.0-or-later
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-- Copyright 2018- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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------------------------------------------------------------------------------
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-- Module Name: sfs_gsim_core - sim
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-- Description: simple frequency synthesis (SIM only!)
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-- simple vhdl model, without Xilinx UNISIM primitives
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--
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-- Dependencies: -
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-- Test bench: -
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-- Target Devices: generic
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-- Tool versions: xst 14.7; viv 2015.4-2018.2; ghdl 0.31-0.34
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--
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-- Revision History:
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-- Date Rev Version Comment
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-- 2018-11-03 1064 1.0 Initial version (derived from s7_cmt_sfs_gsim)
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use work.slvtypes.all;
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entity sfs_gsim_core is -- frequency synthesis for simulation
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generic (
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VCO_DIVIDE : positive := 1; -- vco clock divide
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VCO_MULTIPLY : positive := 1; -- vco clock multiply
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OUT_DIVIDE : positive := 1); -- output divide
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port (
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CLKIN : in slbit; -- clock input
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CLKFX : out slbit; -- clock output (synthesized freq.)
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LOCKED : out slbit -- pll/mmcm locked
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);
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end sfs_gsim_core;
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architecture sim of sfs_gsim_core is
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signal CLK_DIVPULSE : slbit := '0';
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signal CLKOUT_PERIOD : Delay_length := 0 ns;
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signal R_CLKOUT : slbit := '0';
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signal R_LOCKED : slbit := '0';
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begin
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proc_clkin : process (CLKIN)
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variable t_lastclkin : time := 0 ns;
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variable t_lastperiod : Delay_length := 0 ns;
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variable t_period : Delay_length := 0 ns;
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variable nclkin : integer := 1;
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begin
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if CLKIN'event then
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if CLKIN = '1' then -- if CLKIN rising edge
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if t_lastclkin > 0 ns then
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t_lastperiod := t_period;
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t_period := now - t_lastclkin;
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CLKOUT_PERIOD <= (t_period * VCO_DIVIDE * OUT_DIVIDE) / VCO_MULTIPLY;
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if t_lastperiod > 0 ns and abs(t_period-t_lastperiod) > 1 ps then
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report "sfs_gsim_core: CLKIN unstable" severity warning;
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end if;
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end if;
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t_lastclkin := now;
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if t_period > 0 ns then
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nclkin := nclkin - 1;
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if nclkin <= 0 then
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nclkin := VCO_DIVIDE * OUT_DIVIDE;
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CLK_DIVPULSE <= '1';
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R_LOCKED <= '1';
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end if;
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end if;
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else -- if CLKIN falling edge
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CLK_DIVPULSE <= '0';
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end if;
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end if;
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end process proc_clkin;
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proc_clkout : process
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begin
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loop
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wait until CLK_DIVPULSE = '1';
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for i in 1 to VCO_MULTIPLY loop
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R_CLKOUT <= '1';
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wait for CLKOUT_PERIOD/2;
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R_CLKOUT <= '0';
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if i /= VCO_MULTIPLY then
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wait for CLKOUT_PERIOD/2;
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end if;
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end loop; -- i
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end loop;
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end process proc_clkout;
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CLKFX <= R_CLKOUT;
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LOCKED <= R_LOCKED;
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end sim;
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