mirror of
https://github.com/wfjm/w11.git
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cb7b906089
- sys_tst_sram_arty: add system and tb - sramif_mig_arty: add SRAM to DDR via MIG adapter for arty - cdc_pulse: add clock domain crossing for a slowly changing value - cdc_vector_s0: add ENA port (now used in cdc_pulse) - tst_mig/util.tcl: test_rwait: add optional lena argument - viv_tools_build.tcl: downgrade SSN critical warnings to warnings
106 lines
2.8 KiB
VHDL
106 lines
2.8 KiB
VHDL
-- $Id: cdc_value.vhd 1101 2019-01-02 21:22:37Z mueller $
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--
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-- Copyright 2016-2019 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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-- This program is free software; you may redistribute and/or modify it under
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-- the terms of the GNU General Public License as published by the Free
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-- Software Foundation, either version 3, or (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful, but
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-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
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-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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-- for complete details.
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--
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------------------------------------------------------------------------------
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-- Module Name: cdc_value - syn
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-- Description: clock domain crossing for a slowly changing value
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--
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-- Dependencies: cdc_pulse
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-- cdc_vector_s0
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-- Test bench: -
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-- Target Devices: generic
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-- Tool versions: viv 2017.2; ghdl 0.34
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-- Revision History:
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-- Date Rev Version Comment
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-- 2019-01-02 1101 2.0 reinplement using cdc_pulse and cdc_vector_s0
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-- 2016-04-08 459 1.0 Initial version
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--
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use work.slvtypes.all;
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use work.cdclib.all;
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entity cdc_value is -- cdc for value (slow change)
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generic (
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DWIDTH : positive := 16); -- data port width
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port (
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CLKI : in slbit; -- I|input clock
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CLKO : in slbit; -- O|output clock
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DI : in slv(DWIDTH-1 downto 0); -- I|input data
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DO : out slv(DWIDTH-1 downto 0); -- O|output data
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UPDT : out slbit -- O|output data updated
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);
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end entity cdc_value;
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architecture syn of cdc_value is
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subtype d_range is integer range DWIDTH-1 downto 0;
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signal R_DI : slv(d_range) := (others=>'0');
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signal R_UPDT : slbit := '0';
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signal PULSE_PIN : slbit := '0';
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signal PULSE_BUSY : slbit := '0';
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signal PULSE_POUT : slbit := '0';
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begin
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CDC_ENA: cdc_pulse
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generic map (
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POUT_SINGLE => true,
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BUSY_WACK => true)
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port map (
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CLKM => CLKI,
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RESET => '0',
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CLKS => CLKO,
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PIN => PULSE_PIN,
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BUSY => PULSE_BUSY,
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POUT => PULSE_POUT
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);
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CDC_DOUT : cdc_vector_s0
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generic map (
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DWIDTH => DWIDTH)
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port map (
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CLKO => CLKO,
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ENA => PULSE_POUT,
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DI => R_DI,
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DO => DO
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);
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PULSE_PIN <= not PULSE_BUSY;
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proc_clki: process (CLKI)
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begin
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if rising_edge(CLKI) then
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if PULSE_PIN = '1' then
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R_DI <= DI;
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end if;
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end if;
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end process proc_clki;
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proc_clko: process (CLKO)
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begin
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if rising_edge(CLKO) then
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R_UPDT <= PULSE_POUT;
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end if;
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end process proc_clko;
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UPDT <= R_UPDT;
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end syn;
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