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233 lines
7.2 KiB
VHDL
233 lines
7.2 KiB
VHDL
-- $Id: tst_serloop.vhd 1203 2019-08-19 21:41:03Z mueller $
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-- SPDX-License-Identifier: GPL-3.0-or-later
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-- Copyright 2011-2019 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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------------------------------------------------------------------------------
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-- Module Name: tst_serloop - syn
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-- Description: simple stand-alone tester for serport components
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--
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-- Dependencies: -
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-- Test bench: -
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--
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-- Target Devices: generic
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-- Tool versions: ise 13.1-14.7; viv 2014.4-2019.1; ghdl 0.29-0.36
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--
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-- Revision History:
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-- Date Rev Version Comment
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-- 2019-08-17 1203 1.0.3 fix for ghdl V0.36 -Whide warnings
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-- 2011-12-10 438 1.0.2 clr fecnt when abact; add rxui(cnt|dat) regs
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-- 2011-12-09 437 1.0.1 rename serport stat->moni port
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-- 2011-11-06 420 1.0 Initial version
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-- 2011-10-14 416 0.5 First draft
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.slvtypes.all;
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use work.serportlib.all;
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use work.tst_serlooplib.all;
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-- ----------------------------------------------------------------------------
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entity tst_serloop is -- tester for serport components
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port (
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CLK : in slbit; -- clock
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RESET : in slbit; -- reset
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CE_MSEC : in slbit; -- msec pulse
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HIO_CNTL : in hio_cntl_type; -- humanio controls
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HIO_STAT : out hio_stat_type; -- humanio status
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SER_MONI : in serport_moni_type; -- serport monitor
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RXDATA : in slv8; -- receiver data out
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RXVAL : in slbit; -- receiver data valid
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RXHOLD : out slbit; -- receiver data hold
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TXDATA : out slv8; -- transmit data in
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TXENA : out slbit; -- transmit data enable
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TXBUSY : in slbit -- transmit busy
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);
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end tst_serloop;
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architecture syn of tst_serloop is
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type regs_type is record
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rxdata : slv8; -- next rx char
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txdata : slv8; -- next tx char
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rxfecnt : slv16; -- rx frame error counter
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rxoecnt : slv16; -- rx overrun error counter
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rxsecnt : slv16; -- rx sequence error counter
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rxcnt : slv32; -- rx char counter
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txcnt : slv32; -- tx char counter
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rxuicnt : slv8; -- rx unsolicited input counter
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rxuidat : slv8; -- rx unsolicited input data
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rxokcnt : slv16; -- rxok 1->0 transition counter
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txokcnt : slv16; -- txok 1->0 transition counter
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rxok_1 : slbit; -- rxok last cycle
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txok_1 : slbit; -- txok last cycle
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rxthrottle : slbit; -- rx throttle flag
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end record regs_type;
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constant regs_init : regs_type := (
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(others=>'0'), -- rxdata
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(others=>'0'), -- txdata
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(others=>'0'), -- rxfecnt
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(others=>'0'), -- rxoecnt
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(others=>'0'), -- rxsecnt
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(others=>'0'), -- rxcnt
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(others=>'0'), -- txcnt
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(others=>'0'), -- rxuicnt
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(others=>'0'), -- rxuidat
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(others=>'0'), -- rxokcnt
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(others=>'0'), -- txokcnt
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'0','0', -- rxok_1,txok_1
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'0' -- rxthrottle
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);
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signal R_REGS : regs_type := regs_init; -- state registers
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signal N_REGS : regs_type := regs_init; -- next value state regs
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begin
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proc_regs: process (CLK)
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begin
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if rising_edge(CLK) then
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if RESET = '1' then
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R_REGS <= regs_init;
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else
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R_REGS <= N_REGS;
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end if;
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end if;
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end process proc_regs;
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proc_next: process (R_REGS, CE_MSEC, HIO_CNTL, SER_MONI,
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RXDATA, RXVAL, TXBUSY)
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variable r : regs_type := regs_init;
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variable n : regs_type := regs_init;
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variable irxhold : slbit := '1';
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variable itxena : slbit := '0';
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variable itxdata : slv8 := (others=>'0');
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variable skipxon : slbit := '0';
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function nextchar(pskipxon: in slbit; pdata: in slv8) return slv8 is
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variable inc : slv8 := (others=>'0');
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begin
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inc := "00000001";
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if pskipxon='1' and (pdata=c_serport_xon or pdata=c_serport_xoff) then
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inc := "00000010";
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end if;
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return slv(unsigned(pdata)+unsigned(inc));
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end function nextchar;
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begin
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r := R_REGS;
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n := R_REGS;
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irxhold := '1';
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itxena := '0';
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itxdata := RXDATA;
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if HIO_CNTL.mode = c_mode_txblast then
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itxdata := r.txdata;
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end if;
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skipxon := '0';
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if HIO_CNTL.enaxon='1' and HIO_CNTL.enaesc='0' then
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skipxon := '1';
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end if;
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if HIO_CNTL.enathrottle = '1' then
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if CE_MSEC = '1' then
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n.rxthrottle := not r.rxthrottle;
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end if;
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else
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n.rxthrottle := '0';
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end if;
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case HIO_CNTL.mode is
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when c_mode_idle =>
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null;
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when c_mode_rxblast =>
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if RXVAL='1' and r.rxthrottle='0' then
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irxhold := '0';
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if RXDATA /= r.rxdata then
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n.rxsecnt := slv(unsigned(r.rxsecnt) + 1);
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end if;
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n.rxdata := nextchar(skipxon, RXDATA);
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end if;
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when c_mode_txblast =>
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if TXBUSY = '0' then
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itxena := '1';
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n.txdata := nextchar(skipxon, r.txdata);
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end if;
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irxhold := '0';
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if RXVAL = '1' then
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n.rxuicnt := slv(unsigned(r.rxuicnt) + 1);
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n.rxuidat := RXDATA;
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end if;
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when c_mode_loop =>
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if RXVAL='1' and r.rxthrottle='0' and TXBUSY = '0' then
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irxhold := '0';
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itxena := '1';
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end if;
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when others => null;
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end case;
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if SER_MONI.abact = '1' then -- if auto bauder active
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n.rxfecnt := (others=>'0'); -- reset frame error counter
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else -- otherwise
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if SER_MONI.rxerr = '1' then -- count rx frame errors
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n.rxfecnt := slv(unsigned(r.rxfecnt) + 1);
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end if;
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end if;
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if SER_MONI.rxovr = '1' then
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n.rxoecnt := slv(unsigned(r.rxoecnt) + 1);
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end if;
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if RXVAL='1' and irxhold='0' then
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n.rxcnt := slv(unsigned(r.rxcnt) + 1);
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end if;
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if itxena = '1' then
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n.txcnt := slv(unsigned(r.txcnt) + 1);
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end if;
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n.rxok_1 := SER_MONI.rxok;
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n.txok_1 := SER_MONI.txok;
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if SER_MONI.rxok='0' and r.rxok_1='1' then
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n.rxokcnt := slv(unsigned(r.rxokcnt) + 1);
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end if;
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if SER_MONI.txok='0' and r.txok_1='1' then
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n.txokcnt := slv(unsigned(r.txokcnt) + 1);
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end if;
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N_REGS <= n;
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RXHOLD <= irxhold;
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TXENA <= itxena;
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TXDATA <= itxdata;
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HIO_STAT.rxfecnt <= r.rxfecnt;
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HIO_STAT.rxoecnt <= r.rxoecnt;
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HIO_STAT.rxsecnt <= r.rxsecnt;
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HIO_STAT.rxcnt <= r.rxcnt;
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HIO_STAT.txcnt <= r.txcnt;
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HIO_STAT.rxuicnt <= r.rxuicnt;
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HIO_STAT.rxuidat <= r.rxuidat;
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HIO_STAT.rxokcnt <= r.rxokcnt;
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HIO_STAT.txokcnt <= r.txokcnt;
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end process proc_next;
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end syn;
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