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100 lines
3.4 KiB
VHDL
100 lines
3.4 KiB
VHDL
-- $Id: ib_sres_or_mon.vhd 984 2018-01-02 20:56:27Z mueller $
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--
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-- Copyright 2010- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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-- This program is free software; you may redistribute and/or modify it under
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-- the terms of the GNU General Public License as published by the Free
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-- Software Foundation, either version 3, or (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful, but
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-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
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-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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-- for complete details.
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--
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------------------------------------------------------------------------------
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-- Module Name: ib_sres_or_mon - sim
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-- Description: ibus result or monitor
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--
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-- Dependencies: -
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-- Test bench: -
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-- Tool versions: ghdl 0.29-0.31
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--
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-- Revision History:
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-- Date Rev Version Comment
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-- 2010-10-28 336 1.0.1 log errors only if now>0ns (drop startup glitches)
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-- 2010-10-23 335 1.0 Initial version (derived from rritb_sres_or_mon)
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_textio.all;
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use std.textio.all;
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use work.slvtypes.all;
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use work.iblib.all;
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-- ----------------------------------------------------------------------------
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entity ib_sres_or_mon is -- ibus result or monitor
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port (
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IB_SRES_1 : in ib_sres_type; -- ib_sres input 1
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IB_SRES_2 : in ib_sres_type; -- ib_sres input 2
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IB_SRES_3 : in ib_sres_type := ib_sres_init; -- ib_sres input 3
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IB_SRES_4 : in ib_sres_type := ib_sres_init -- ib_sres input 4
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);
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end ib_sres_or_mon;
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architecture sim of ib_sres_or_mon is
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begin
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proc_comb : process (IB_SRES_1, IB_SRES_2, IB_SRES_3, IB_SRES_4)
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constant dzero : slv16 := (others=>'0');
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variable oline : line;
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variable nack : integer := 0;
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variable nbusy : integer := 0;
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variable ndout : integer := 0;
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begin
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nack := 0;
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nbusy := 0;
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ndout := 0;
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if IB_SRES_1.ack /= '0' then nack := nack + 1; end if;
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if IB_SRES_2.ack /= '0' then nack := nack + 1; end if;
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if IB_SRES_3.ack /= '0' then nack := nack + 1; end if;
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if IB_SRES_4.ack /= '0' then nack := nack + 1; end if;
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if IB_SRES_1.busy /= '0' then nbusy := nbusy + 1; end if;
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if IB_SRES_2.busy /= '0' then nbusy := nbusy + 1; end if;
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if IB_SRES_3.busy /= '0' then nbusy := nbusy + 1; end if;
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if IB_SRES_4.busy /= '0' then nbusy := nbusy + 1; end if;
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if IB_SRES_1.dout /= dzero then ndout := ndout + 1; end if;
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if IB_SRES_2.dout /= dzero then ndout := ndout + 1; end if;
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if IB_SRES_3.dout /= dzero then ndout := ndout + 1; end if;
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if IB_SRES_4.dout /= dzero then ndout := ndout + 1; end if;
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if now > 0 ns and (nack>1 or nbusy>1 or ndout>1) then
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write(oline, now, right, 12);
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if nack > 1 then
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write(oline, string'(" #ack="));
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write(oline, nack);
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end if;
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if nbusy > 1 then
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write(oline, string'(" #busy="));
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write(oline, nbusy);
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end if;
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if ndout > 1 then
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write(oline, string'(" #dout="));
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write(oline, ndout);
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end if;
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write(oline, string'(" FAIL in "));
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write(oline, ib_sres_or_mon'path_name);
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writeline(output, oline);
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end if;
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end process proc_comb;
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end sim;
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