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155 lines
4.6 KiB
VHDL
155 lines
4.6 KiB
VHDL
-- $Id: rbd_timer.vhd 984 2018-01-02 20:56:27Z mueller $
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--
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-- Copyright 2010-2014 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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-- This program is free software; you may redistribute and/or modify it under
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-- the terms of the GNU General Public License as published by the Free
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-- Software Foundation, either version 3, or (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful, but
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-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
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-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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-- for complete details.
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--
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------------------------------------------------------------------------------
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-- Module Name: rbd_timer - syn
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-- Description: rbus dev: usec precision timer
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--
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-- Dependencies: -
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--
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-- Test bench: -
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--
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-- Target Devices: generic
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-- Tool versions: xst 12.1-14.7; viv 2014.4-2015.4; ghdl 0.29-0.33
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--
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-- Synthesized (xst):
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-- Date Rev ise Target flop lutl lutm slic t peri
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-- 2010-12-29 351 12.1 M53d xc3s1000-4 19 63 - 34 s 7.6
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--
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-- Revision History:
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-- Date Rev Version Comment
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-- 2014-08-15 583 4.0 rb_mreq addr now 16 bit
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-- 2011-11-19 427 1.0.1 now numeric_std clean
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-- 2010-12-29 351 1.0 Initial version
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------------------------------------------------------------------------------
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--
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-- rbus registers:
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--
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-- Addr Bits Name r/w/f Function
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-- 0 time r/w/- Timer register
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-- w: if > 0 timer is running
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--
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.slvtypes.all;
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use work.rblib.all;
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entity rbd_timer is -- rbus dev: usec precision timer
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generic (
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RB_ADDR : slv16 := (others=>'0'));
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port (
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CLK : in slbit; -- clock
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CE_USEC : in slbit; -- usec pulse
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RESET : in slbit; -- reset
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RB_MREQ : in rb_mreq_type; -- rbus: request
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RB_SRES : out rb_sres_type; -- rbus: response
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DONE : out slbit; -- 1 cycle pulse when expired
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BUSY : out slbit -- timer running
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);
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end entity rbd_timer;
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architecture syn of rbd_timer is
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type regs_type is record -- state registers
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rbsel : slbit; -- rbus select
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timer : slv16; -- timer value
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timer_act : slbit; -- timer active flag
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timer_end : slbit; -- timer done flag
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end record regs_type;
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constant regs_init : regs_type := (
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'0', -- rbsel
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(others=>'0'), -- timer
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'0','0' -- timer_act,timer_end
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);
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signal R_REGS : regs_type := regs_init;
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signal N_REGS : regs_type := regs_init;
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begin
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proc_regs: process (CLK)
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begin
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if rising_edge(CLK) then
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if RESET = '1' then
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R_REGS <= regs_init;
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else
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R_REGS <= N_REGS;
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end if;
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end if;
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end process proc_regs;
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proc_next : process (R_REGS, CE_USEC, RB_MREQ)
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variable r : regs_type := regs_init;
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variable n : regs_type := regs_init;
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variable irb_ack : slbit := '0';
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variable irb_dout : slv16 := (others=>'0');
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begin
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r := R_REGS;
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n := R_REGS;
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irb_ack := '0';
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irb_dout := (others=>'0');
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-- rbus address decoder
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n.rbsel := '0';
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if RB_MREQ.aval='1' and RB_MREQ.addr=RB_ADDR then
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n.rbsel := '1';
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end if;
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-- rbus transactions
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if r.rbsel = '1' then
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irb_ack := RB_MREQ.re or RB_MREQ.we;
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if RB_MREQ.we = '1' then
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n.timer := RB_MREQ.din;
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n.timer_act := '1';
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end if;
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if RB_MREQ.re = '1' then
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irb_dout := r.timer;
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end if;
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end if;
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-- timer logic
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-- count down when active and 'on-the-usec'
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n.timer_end := '0'; -- ensure end is 1 cycle pulse
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if CE_USEC = '1' then -- if at usec
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if r.timer_act = '1' then -- if timer active
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if unsigned(r.timer) = 0 then -- if timer at end
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n.timer_act := '0'; -- mark unactive
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n.timer_end := '1'; -- send end marker
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else -- else: timer not at end
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n.timer := slv(unsigned(r.timer) - 1); -- decrement
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end if;
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end if;
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end if;
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N_REGS <= n;
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RB_SRES.dout <= irb_dout;
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RB_SRES.ack <= irb_ack;
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RB_SRES.err <= '0';
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RB_SRES.busy <= '0';
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DONE <= r.timer_end;
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BUSY <= r.timer_act;
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end process proc_next;
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end syn;
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