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- pdp11_sequencer.vhd: CPUERR cleared by CRESET - mminki.mac: added, procedure to initialize MMU, kernel I space only - test_w11a_cpuerr.tcl: added, test cpuerr register - added more README's - editorial changes
224 lines
7.9 KiB
Tcl
224 lines
7.9 KiB
Tcl
# $Id: test_w11a_cpuerr.tcl 831 2016-12-27 16:51:12Z mueller $
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#
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# Copyright 2016- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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# License disclaimer see License.txt in $RETROBASE directory
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#
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# Revision History:
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# Date Rev Version Comment
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# 2016-12-27 831 1.0 Initial version
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#
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# Test cpuerr register
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#
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# ----------------------------------------------------------------------------
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rlc log "test_w11a_cpuerr: test cpuerr register"
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rlc log " test basic CPUERR semantics"
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$cpu ldasm -lst lst -sym sym {
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.include |lib/defs_cpu.mac|
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.include |lib/defs_reg70.mac|
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.include |lib/defs_mmu.mac|
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;
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.include |lib/vec_cpucatch.mac|
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;
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. = 1000
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stack:
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start:
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;
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; test 001: first test that any write will clear cpuerr ----------------------
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; that test also conveniently erases any pre-history
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;
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mov #177777,@#cpuerr ; clear cpuerr
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mov #001,(r5)+ ; tag
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mov @#cpuerr,(r5)+ ; val
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;
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; test 002: odd address abort, will set bit cp.aer ---------------------------
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;
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mov @#v..iit,saviit ; save old handler
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mov #h.iit,@#v..iit ; setup handler
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mov #t.002,r4 ; setup continuation address
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mov #1,r0 ; r0 points to odd address
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tst (r0) ; access
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; !! will trap to 004 and set 000100 !!
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halt ; blocker
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t.002:
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;
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; test 003: clear cpuerr again (now it's really set) -------------------------
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;
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mov #177777,@#cpuerr ; clear cpuerr
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mov #003,(r5)+ ; tag
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mov @#cpuerr,(r5)+ ; val
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;
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; test 004: non-existent memory abort, will set bit cp.nxm -------------------
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;
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; The address space jusr below the I/O page is never accessible in the
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; w11 (the 11/70 has ubmap window in this addess space).
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; So setup MMU kernel I space AR(6) to point to the 8 kbyte below I/O page
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; don't clear CPUERR at end of test !
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;
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jsr pc, mminki ; init MMU, kernel I space only
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mov #177400,@#kipar+014 ; kipar(6): to page below I/O page
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mov #m3.e22,@#ssr3 ; enable 22bit
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mov #m0.ena,@#ssr0 ; enable MMU
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;
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mov #t.004,r4 ; setup continuation address
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mov #140000,r0 ; r0 points to non-existent memory
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tst (r0) ; access
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; !! will trap to 004 and set 000040 !!
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halt ; blocker
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t.004: clr @#ssr0 ; disable MMU
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;
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; test 005: I/O bus timeout abort; will set bit cp.ito -----------------------
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;
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; The lowest I/O page address 160000 not occupied by a device in the w11.
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; Since CPUERR wasn't cleared after previous test the error bits will
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; accumulate
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;
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mov #t.005,r4 ; setup continuation address
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mov #160000,r0 ; r0 points to non-existent device
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tst (r0) ; access
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; !! will trap to 004 and set 000020 !!
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halt ; blocker
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t.005:
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;
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; test 006: HALT in user mode; will set bit cp.hlt ---------------------------
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;
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mov #h.hlt,@#v..iit ; setup handler
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mov #cp.cmu!cp.pmu,@#cp.psw ; psw: cmode=pmode=11 (user)
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mov #t.006,r4 ; setup continuation address
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1$: halt
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br 1$ ; blocker
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t.006:
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; clear cpuerr again
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mov #177777,@#cpuerr ; clear cpuerr
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mov #006,(r5)+ ; tag
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mov @#cpuerr,(r5)+ ; val
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;
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; test 007: yellow stack trap; will set bit cp.ysv ---------------------------
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;
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mov #h.iit,@#v..iit ; setup handler
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mov #t.007,r4 ; setup continuation address
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mov #000400,sp ; set stack into 'yellow' zone
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clr -(sp) ; and push to stack
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; push will be done plus a trap !
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t.007:
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;
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; test 010: 2nd yellow stack trap with CPUERR set should *not* trap ----------
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;
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mov saviit,@#v..iit ; restore blocker handler
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clr -(sp) ; and push to stack
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; push will be done and no trap !
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mov #010,(r5)+ ; tag
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mov sp,(r5)+ ; val
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; clear cpuerr again
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mov #177777,@#cpuerr ; clear cpuerr
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mov #010,(r5)+ ; tag
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mov @#cpuerr,(r5)+ ; val
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;
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; test 011: red stack trap from odd stack; will set bit cp.aer and cp.rsv ----
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;
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mov #h.rsv,@#v..iit ; setup handler (will also reset stack)
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mov #t.011,r4 ; setup continuation address
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mov #001001,sp ; set stack odd kernel stack
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clr -(sp) ; and push to stack
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; cause 'red stack' and set SP=004
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t.011:
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; clear cpuerr again
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mov #177777,@#cpuerr ; clear cpuerr
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mov #011,(r5)+ ; tag
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mov @#cpuerr,(r5)+ ; val
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;
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; end of tests ---------------------------------------------------------------
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;
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halt
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stop:
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;
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h.iit: mov r4,(r5)+ ; tag
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mov @#cpuerr,(r5)+ ; val
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mov r4,(sp) ; set return PC
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rti
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;
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h.hlt: mov r4,(r5)+ ; tag
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mov @#cpuerr,(r5)+ ; val
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mov r4,(sp) ; set return PC
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clr 2(sp) ; set return PS (kernel mode again)
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rti
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;
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h.rsv: mov r4,(r5)+ ; tag
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mov @#cpuerr,(r5)+ ; val
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mov #1000,sp ; reset stack
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clr -(sp) ; PS = kernel mode
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mov r4,-(sp) ; PC = continuation address
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rti
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;
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saviit: .word 0
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data: .blkw 12.*2.
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.word 177777
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;
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; support procedures
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;
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.include |lib/mminki.mac|
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}
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# puts $lst
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# parray sym
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# code register pre/post conditions beyond defaults
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# r5 #data -> #data+12*2*2
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rw11::asmrun $cpu sym r5 $sym(data)
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rw11::asmwait $cpu sym
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rw11::asmtreg $cpu r1 0 \
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r2 0 \
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r3 0 \
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r5 [expr {$sym(data) + 12*2*2}] \
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sp $sym(stack)
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# data: tag val pairs
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rw11::asmtmem $cpu $sym(data) \
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[list 001 0000000 \
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$sym(t.002) [regbld rw11::CPUERR adderr] \
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003 0000000 \
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$sym(t.004) [regbld rw11::CPUERR nxm] \
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$sym(t.005) [regbld rw11::CPUERR nxm iobto] \
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$sym(t.006) 0000260 \
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006 0000000 \
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$sym(t.007) [regbld rw11::CPUERR ysv] \
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010 0000374 \
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010 0000000 \
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$sym(t.011) [regbld rw11::CPUERR adderr rsv] \
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011 0000000 \
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0177777 ]
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# ----------------------------------------------------------------------------
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rlc log " test basic CPUERR reset via creset"
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# use minmal code to set CPUERR: odd address abort against vector catcher
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$cpu ldasm -lst lst -sym sym {
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. = 000004
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v..iit: .word v..iit+2 ; vec 4
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.word 0
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stop:
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;
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. = 1000
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stack:
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start:
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;
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mov #1,r0 ; r0 points to odd address
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tst (r0) ; access
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}
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rw11::asmrun $cpu sym
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rw11::asmwait $cpu sym
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rw11::asmtreg $cpu r1 0 \
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r2 0 \
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r3 0 \
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r5 0 \
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sp [expr $sym(stack) - 4]
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# now test whether creset clears CPUERR
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rw11::asmtmem $cpu $rw11::A_CPUERR [regbld rw11::CPUERR adderr]
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cpu0 cp -creset
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rw11::asmtmem $cpu $rw11::A_CPUERR 0
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