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154 lines
5.9 KiB
VHDL
154 lines
5.9 KiB
VHDL
-- $Id: ib_intmap.vhd 1181 2019-07-08 17:00:50Z mueller $
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-- SPDX-License-Identifier: GPL-3.0-or-later
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-- Copyright 2006-2019 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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------------------------------------------------------------------------------
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-- Module Name: ib_intmap - syn
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-- Description: pdp11: external interrupt mapper (15 line)
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--
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-- Dependencies: -
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-- Test bench: tb/tb_pdp11_core (implicit)
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-- Target Devices: generic
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-- Tool versions: ise 8.2-14.7; viv 2014.4-2017.2; ghdl 0.18-0.35
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--
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-- Synthesized:
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-- Date Rev viv Target flop lutl lutm bram slic MHz
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-- 2016-05-26 641 2016.4 xc7a100t-1 0 30 0 0 - -
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-- 2015-02-22 641 i 14.7 xc6slx16-2 0 20 0 0 9 -
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--
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-- Revision History:
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-- Date Rev Version Comment
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-- 2019-04-23 1136 1.2 BUGFIX: ensure ACK send to correct device
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-- 2011-11-18 427 1.2.2 now numeric_std clean
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-- 2008-08-22 161 1.2.1 renamed pdp11_ -> ib_; use iblib
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-- 2008-01-20 112 1.2 add INTMAP generic to externalize config
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-- 2008-01-06 111 1.1 add EI_ACK output lines, remove EI_LINE
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-- 2007-10-12 88 1.0.2 avoid ieee.std_logic_unsigned, use cast to unsigned
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-- 2007-06-14 56 1.0.1 Use slvtypes.all
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-- 2007-05-12 26 1.0 Initial version
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.slvtypes.all;
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use work.iblib.all;
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-- ----------------------------------------------------------------------------
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entity ib_intmap is -- external interrupt mapper
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generic (
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INTMAP : intmap_array_type := intmap_array_init);
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port (
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CLK : in slbit; -- clock
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EI_REQ : in slv16_1; -- interrupt request lines
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EI_ACKM : in slbit; -- interrupt acknowledge (from master)
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EI_ACK : out slv16_1; -- interrupt acknowledge (to requestor)
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EI_PRI : out slv3; -- interrupt priority
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EI_VECT : out slv9_2 -- interrupt vector
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);
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end ib_intmap;
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architecture syn of ib_intmap is
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signal EI_LINE : slv4 := (others=>'0'); -- external interrupt line
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signal R_LINE : slv4 := (others=>'0'); -- line on last cycle
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type intp_type is array (15 downto 0) of slv3;
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type intv_type is array (15 downto 0) of slv9;
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constant conf_intp : intp_type :=
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(slv(to_unsigned(INTMAP(15).pri,3)), -- line 15
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slv(to_unsigned(INTMAP(14).pri,3)), -- line 14
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slv(to_unsigned(INTMAP(13).pri,3)), -- line 13
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slv(to_unsigned(INTMAP(12).pri,3)), -- line 12
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slv(to_unsigned(INTMAP(11).pri,3)), -- line 11
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slv(to_unsigned(INTMAP(10).pri,3)), -- line 10
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slv(to_unsigned(INTMAP( 9).pri,3)), -- line 9
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slv(to_unsigned(INTMAP( 8).pri,3)), -- line 8
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slv(to_unsigned(INTMAP( 7).pri,3)), -- line 7
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slv(to_unsigned(INTMAP( 6).pri,3)), -- line 6
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slv(to_unsigned(INTMAP( 5).pri,3)), -- line 5
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slv(to_unsigned(INTMAP( 4).pri,3)), -- line 4
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slv(to_unsigned(INTMAP( 3).pri,3)), -- line 3
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slv(to_unsigned(INTMAP( 2).pri,3)), -- line 2
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slv(to_unsigned(INTMAP( 1).pri,3)), -- line 1
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slv(to_unsigned( 0,3)) -- line 0 (always 0 !!)
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);
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constant conf_intv : intv_type :=
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(slv(to_unsigned(INTMAP(15).vec,9)), -- line 15
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slv(to_unsigned(INTMAP(14).vec,9)), -- line 14
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slv(to_unsigned(INTMAP(13).vec,9)), -- line 13
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slv(to_unsigned(INTMAP(12).vec,9)), -- line 12
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slv(to_unsigned(INTMAP(11).vec,9)), -- line 11
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slv(to_unsigned(INTMAP(10).vec,9)), -- line 10
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slv(to_unsigned(INTMAP( 9).vec,9)), -- line 9
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slv(to_unsigned(INTMAP( 8).vec,9)), -- line 8
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slv(to_unsigned(INTMAP( 7).vec,9)), -- line 7
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slv(to_unsigned(INTMAP( 6).vec,9)), -- line 6
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slv(to_unsigned(INTMAP( 5).vec,9)), -- line 5
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slv(to_unsigned(INTMAP( 4).vec,9)), -- line 4
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slv(to_unsigned(INTMAP( 3).vec,9)), -- line 3
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slv(to_unsigned(INTMAP( 2).vec,9)), -- line 2
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slv(to_unsigned(INTMAP( 1).vec,9)), -- line 1
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slv(to_unsigned( 0,9)) -- line 0 (always 0 !!)
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);
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-- attribute PRIORITY_EXTRACT : string;
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-- attribute PRIORITY_EXTRACT of EI_LINE : signal is "force";
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begin
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EI_LINE <= "1111" when EI_REQ(15)='1' else
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"1110" when EI_REQ(14)='1' else
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"1101" when EI_REQ(13)='1' else
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"1100" when EI_REQ(12)='1' else
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"1011" when EI_REQ(11)='1' else
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"1010" when EI_REQ(10)='1' else
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"1001" when EI_REQ( 9)='1' else
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"1000" when EI_REQ( 8)='1' else
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"0111" when EI_REQ( 7)='1' else
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"0110" when EI_REQ( 6)='1' else
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"0101" when EI_REQ( 5)='1' else
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"0100" when EI_REQ( 4)='1' else
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"0011" when EI_REQ( 3)='1' else
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"0010" when EI_REQ( 2)='1' else
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"0001" when EI_REQ( 1)='1' else
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"0000";
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proc_line: process (CLK)
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begin
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if rising_edge(CLK) then
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R_LINE <= EI_LINE;
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end if;
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end process proc_line;
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-- Note: EI_ACKM comes one cycle after vector is latched ! Therefore
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-- - use EI_LINE to select vector to send to EI_PRI and EI_VECT
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-- - use R_LINE to select EI_ACM line for acknowledge
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proc_intmap : process (EI_LINE, EI_ACKM, R_LINE)
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variable ilinecur : integer := 0;
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variable ilinelst : integer := 0;
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variable iei_ack : slv16 := (others=>'0');
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begin
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ilinecur := to_integer(unsigned(EI_LINE));
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ilinelst := to_integer(unsigned(R_LINE));
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-- send info of currently highest priority request
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EI_PRI <= conf_intp(ilinecur);
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EI_VECT <= conf_intv(ilinecur)(8 downto 2);
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-- route acknowledge back to winner line of last cycle
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iei_ack := (others=>'0');
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if EI_ACKM = '1' then
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iei_ack(ilinelst) := '1';
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end if;
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EI_ACK <= iei_ack(EI_ACK'range);
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end process proc_intmap;
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end syn;
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