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05c7d937c7
- general board support - c7_sram_memctl: SRAM memory controller (incl tb) - is61wv5128bll: simple memory model (incl tb) - sn_humanio_emu_rbus: human IO emulator - 92-retro-usb-persistent.rules: add more board rules - associated changes - sn_humanio_rbus: add stat_rbf_emu (=0); single cycle btn pulses - rgbdrv_analog(_rbus): add ACTLOW generic to invert output polarity - ti_rri: adopt Digilent autodetect for CmodA7 - add systems - tst_rlink: rlink tested - tst_sram: SRAM tester - w11a: w11a system with 672 kB memory (512 SRAM + 160 BRAM)
85 lines
3.6 KiB
VHDL
85 lines
3.6 KiB
VHDL
-- $Id: cmoda7lib.vhd 912 2017-06-11 18:30:03Z mueller $
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--
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-- Copyright 2017- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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-- This program is free software; you may redistribute and/or modify it under
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-- the terms of the GNU General Public License as published by the Free
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-- Software Foundation, either version 2, or at your option any later version.
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--
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-- This program is distributed in the hope that it will be useful, but
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-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
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-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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-- for complete details.
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--
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------------------------------------------------------------------------------
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-- Package Name: cmoda7lib
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-- Description: CmodA7 components
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--
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-- Dependencies: -
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-- Tool versions: viv 2016.4-2017.1; ghdl 0.34
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--
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-- Revision History:
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-- Date Rev Version Comment
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-- 2017-06-11 912 1.1 add c7_sram_memctl
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-- 2017-06-04 906 1.0 Initial version
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use work.slvtypes.all;
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package cmoda7lib is
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component cmoda7_aif is -- CmodA7, abstract iface, base
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port (
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I_CLK12 : in slbit; -- 12 MHz clock
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I_RXD : in slbit; -- receive data (board view)
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O_TXD : out slbit; -- transmit data (board view)
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I_BTN : in slv2; -- c7 buttons
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O_LED : out slv2; -- c7 leds
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O_RGBLED0_N: out slv3 -- c7 rgb-led 0 (act.low)
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);
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end component;
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component cmoda7_sram_aif is -- CmodA7, abstract iface, base+sram
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port (
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I_CLK12 : in slbit; -- 12 MHz clock
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I_RXD : in slbit; -- receive data (board view)
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O_TXD : out slbit; -- transmit data (board view)
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I_BTN : in slv2; -- c7 buttons
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O_LED : out slv2; -- c7 leds
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O_RGBLED0_N: out slv3; -- c7 rgb-led 0 (act.low)
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O_MEM_CE_N : out slbit; -- sram: chip enable (act.low)
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O_MEM_WE_N : out slbit; -- sram: write enable (act.low)
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O_MEM_OE_N : out slbit; -- sram: output enable (act.low)
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O_MEM_ADDR : out slv19; -- sram: address lines
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IO_MEM_DATA : inout slv8 -- sram: data lines
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);
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end component;
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component c7_sram_memctl is -- SRAM controller
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port (
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CLK : in slbit; -- clock
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RESET : in slbit; -- reset
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REQ : in slbit; -- request
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WE : in slbit; -- write enable
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BUSY : out slbit; -- controller busy
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ACK_R : out slbit; -- acknowledge read
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ACK_W : out slbit; -- acknowledge write
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ACT_R : out slbit; -- signal active read
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ACT_W : out slbit; -- signal active write
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ADDR : in slv17; -- address
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BE : in slv4; -- byte enable
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DI : in slv32; -- data in (memory view)
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DO : out slv32; -- data out (memory view)
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O_MEM_CE_N : out slbit; -- sram: chip enable (act.low)
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O_MEM_WE_N : out slbit; -- sram: write enable (act.low)
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O_MEM_OE_N : out slbit; -- sram: output enable (act.low)
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O_MEM_ADDR : out slv19; -- sram: address lines
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IO_MEM_DATA : inout slv8 -- sram: data lines
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);
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end component;
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end package cmoda7lib;
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