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105 lines
4.8 KiB
VHDL
105 lines
4.8 KiB
VHDL
-- $Id: fx2rlinklib.vhd 672 2015-05-02 21:58:28Z mueller $
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--
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-- Copyright 2013-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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-- This program is free software; you may redistribute and/or modify it under
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-- the terms of the GNU General Public License as published by the Free
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-- Software Foundation, either version 2, or at your option any later version.
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--
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-- This program is distributed in the hope that it will be useful, but
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-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
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-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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-- for complete details.
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--
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------------------------------------------------------------------------------
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-- Package Name: fx2rlinklib
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-- Description: Definitions for rlink + fx2 interface combos
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--
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-- Dependencies: -
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-- Tool versions: xst 13.3-14.7; ghdl 0.29-0.31
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--
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-- Revision History:
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-- Date Rev Version Comment
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-- 2015-04-11 666 1.2 rlink_sp1c_fx2: drop ENAESC
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-- 2014-08-28 588 1.1 use new rlink v4 iface generics and 4 bit STAT
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-- 2013-04-20 509 1.0 Initial version
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.slvtypes.all;
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use work.rblib.all;
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use work.rlinklib.all;
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use work.serportlib.all;
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use work.fx2lib.all;
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package fx2rlinklib is
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--
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-- core + fx2 interface combo
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--
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component rlink_sp1c_fx2 is -- rlink_core8+serport_1clk+fx2_ic combo
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generic (
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BTOWIDTH : positive := 5; -- rbus timeout counter width
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RTAWIDTH : positive := 12; -- retransmit buffer address width
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SYSID : slv32 := (others=>'0'); -- rlink system id
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IFAWIDTH : natural := 5; -- ser input fifo addr width (0=none)
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OFAWIDTH : natural := 5; -- ser output fifo addr width (0=none)
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PETOWIDTH : positive := 10; -- fx2 packet end time-out counter width
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CCWIDTH : positive := 5; -- fx2 chunk counter width
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ENAPIN_RLMON : integer := -1; -- SB_CNTL for rlmon (-1=none)
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ENAPIN_RLBMON: integer := -1; -- SB_CNTL for rlbmon (-1=none)
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ENAPIN_RBMON : integer := -1; -- SB_CNTL for rbmon (-1=none)
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CDWIDTH : positive := 13; -- clk divider width
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CDINIT : natural := 15; -- clk divider initial/reset setting
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RBMON_AWIDTH : natural := 0; -- rbmon: buffer size (0=none)
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RBMON_RBADDR : slv16 := slv(to_unsigned(16#ffe8#,16))); -- rbmon: base addr
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port (
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CLK : in slbit; -- clock
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CE_USEC : in slbit; -- 1 usec clock enable
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CE_MSEC : in slbit; -- 1 msec clock enable
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CE_INT : in slbit := '0'; -- rri ato time unit clock enable
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RESET : in slbit; -- reset
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ENAXON : in slbit; -- enable xon/xoff handling
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ENAFX2 : in slbit; -- enable fx2 usage
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RXSD : in slbit; -- receive serial data (board view)
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TXSD : out slbit; -- transmit serial data (board view)
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CTS_N : in slbit := '0'; -- clear to send (act.low, board view)
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RTS_N : out slbit; -- request to send (act.low, board view)
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RB_MREQ : out rb_mreq_type; -- rbus: request
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RB_SRES : in rb_sres_type; -- rbus: response
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RB_LAM : in slv16; -- rbus: look at me
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RB_STAT : in slv4; -- rbus: status flags
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RL_MONI : out rl_moni_type; -- rlink_core: monitor port
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RLB_MONI : out rlb_moni_type; -- rlink 8b: monitor port
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SER_MONI : out serport_moni_type; -- ser: monitor port
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FX2_MONI : out fx2ctl_moni_type; -- fx2: monitor port
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I_FX2_IFCLK : in slbit; -- fx2: interface clock
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O_FX2_FIFO : out slv2; -- fx2: fifo address
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I_FX2_FLAG : in slv4; -- fx2: fifo flags
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O_FX2_SLRD_N : out slbit; -- fx2: read enable (act.low)
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O_FX2_SLWR_N : out slbit; -- fx2: write enable (act.low)
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O_FX2_SLOE_N : out slbit; -- fx2: output enable (act.low)
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O_FX2_PKTEND_N : out slbit; -- fx2: packet end (act.low)
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IO_FX2_DATA : inout slv8 -- fx2: data lines
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);
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end component;
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component ioleds_sp1c_fx2 -- io activity leds for rlink_sp1c_fx2
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port (
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CLK : in slbit; -- clock
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CE_USEC : in slbit; -- 1 usec clock enable
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RESET : in slbit; -- reset
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ENAFX2 : in slbit; -- enable fx2 usage
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RB_SRES : in rb_sres_type; -- rbus: response
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RLB_MONI : in rlb_moni_type; -- rlink 8b: monitor port
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SER_MONI : in serport_moni_type; -- ser: monitor port
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IOLEDS : out slv4 -- 4 bit IO monitor (e.g. for DSP_DP)
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);
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end component;
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end package fx2rlinklib;
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