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674762d6d8
- s7_cmt_1ce1ce: add clock generator block used in many 7-Series designs - sys_gen/*/*: use s7_cmt_1ce1ce in 7-Series designs - tbcore_rlink: wait 40 cycles after CONF_DONE - serport_master_tb: add 100 ps RXSD,TXSD delay to allow clock jitter
This directory sub-tree contains a wide range of support modules and is organized in
| Directory | Content |
|---|---|
| cdclib | modules for clock domain crossing |
| comlib | modules for communication |
| genlib | grab bag of other modules |
| memlib | wrappers for distributed and block RAM; fifos |
| rbus | modules for rbus fabric; some basic rbus devices |
| rlink | rlink interface |
| serport | serial port interface |
| simlib | helper modules for test benches |
| xlib | warppers for some Xilinx components |