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https://github.com/wfjm/w11.git
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05c7d937c7
- general board support - c7_sram_memctl: SRAM memory controller (incl tb) - is61wv5128bll: simple memory model (incl tb) - sn_humanio_emu_rbus: human IO emulator - 92-retro-usb-persistent.rules: add more board rules - associated changes - sn_humanio_rbus: add stat_rbf_emu (=0); single cycle btn pulses - rgbdrv_analog(_rbus): add ACTLOW generic to invert output polarity - ti_rri: adopt Digilent autodetect for CmodA7 - add systems - tst_rlink: rlink tested - tst_sram: SRAM tester - w11a: w11a system with 672 kB memory (512 SRAM + 160 BRAM)
63 lines
2.2 KiB
Tcl
63 lines
2.2 KiB
Tcl
# -*- tcl -*-
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# $Id: cmoda7_pins.xdc 906 2017-06-04 21:59:13Z mueller $
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#
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# Copyright 2017- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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# License disclaimer see License.txt in $RETROBASE directory
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#
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# Digilent CmodA7 core functionality
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# - Configuration setup
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# - config voltage
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# - enable bitstream timestamp
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# - Pin Locks for
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# - USB UART
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# - human I/O (sbuttons, leds)
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#
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# Revision History:
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# Date Rev Version Comment
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# 2017-06-04 906 1.0 Initial version
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#
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# config setup --------------------------------------------------------------
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set_property CFGBVS VCCO [current_design]
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set_property CONFIG_VOLTAGE 3.3 [current_design]
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set_property BITSTREAM.CONFIG.USR_ACCESS TIMESTAMP [current_design]
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# clocks -- in bank 14 ------------------------------------------------------
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set_property PACKAGE_PIN l17 [get_ports {I_CLK12}]
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set_property IOSTANDARD LVCMOS33 [get_ports {I_CLK12}]
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#
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# USB UART Interface -- in bank 14 ------------------------------------------
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set_property PACKAGE_PIN j17 [get_ports {I_RXD}]
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set_property PACKAGE_PIN j18 [get_ports {O_TXD}]
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set_property IOSTANDARD LVCMOS33 [get_ports {I_RXD O_TXD}]
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set_property DRIVE 12 [get_ports {O_TXD}]
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set_property SLEW SLOW [get_ports {O_TXD}]
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#
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# buttons -- in bank 16 -----------------------------------------------------
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set_property PACKAGE_PIN a18 [get_ports {I_BTN[0]}]
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set_property PACKAGE_PIN b18 [get_ports {I_BTN[1]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {I_BTN[*]}]
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#
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# LEDs -- in bank 16 --------------------------------------------------------
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set_property PACKAGE_PIN a17 [get_ports {O_LED[0]}]
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set_property PACKAGE_PIN c16 [get_ports {O_LED[1]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {O_LED[*]}]
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set_property DRIVE 12 [get_ports {O_LED[*]}]
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set_property SLEW SLOW [get_ports {O_LED[*]}]
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#
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# RGB-LED -- in bank 16 -----------------------------------------------------
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set_property PACKAGE_PIN c17 [get_ports {O_RGBLED0_N[0]}]
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set_property PACKAGE_PIN b16 [get_ports {O_RGBLED0_N[1]}]
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set_property PACKAGE_PIN b17 [get_ports {O_RGBLED0_N[2]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {O_RGBLED0_N[*]}]
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set_property DRIVE 12 [get_ports {O_RGBLED0_N[*]}]
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set_property SLEW SLOW [get_ports {O_RGBLED0_N[*]}]
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