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107 lines
3.4 KiB
VHDL
107 lines
3.4 KiB
VHDL
-- $Id: ib_rlim_gen.vhd 1181 2019-07-08 17:00:50Z mueller $
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-- SPDX-License-Identifier: GPL-3.0-or-later
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-- Copyright 2019- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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------------------------------------------------------------------------------
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-- Module Name: ib_rlim_gen - syn
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-- Description: ibus rate limter - master
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--
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-- Dependencies: -
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-- Test bench: -
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-- Target Devices: generic
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-- Tool versions: ise 14.7; viv 2017.2; ghdl 0.35
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--
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-- Revision History:
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-- Date Rev Version Comment
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-- 2019-04-14 1131 1.1 add CPUSUSP port; RLIM_CEV now slv8
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-- 2019-03-17 1123 1.0 Initial version
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-- 2019-03-15 1122 0.1 First draft
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--
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-- Notes:
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-- cev scale rate in slv
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-- (0) none 8 clock cycles
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-- (1) 1: 1 8 usec 125.0 kHz
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-- (2) 1: 2 16 usec 62.5 kHz
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-- (3) 1: 4 32 usec 31.2 kHz
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-- (4) 1: 8 64 usec 15.6 kHz
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-- (5) 1: 32 256 usec 3.9 kHz
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-- (6) 1: 64 512 usec 2.0 kHz
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-- (7) 1:128 1024 usec 1.0 kHz
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.slvtypes.all;
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-- ----------------------------------------------------------------------------
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entity ib_rlim_gen is -- ibus rate limter - master
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port (
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CLK : in slbit; -- clock
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CE_USEC : in slbit; -- usec pulse
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RESET : in slbit; -- system reset
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CPUSUSP : in slbit; -- cpu suspended
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RLIM_CEV : out slv8 -- clock enable vector
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);
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end ib_rlim_gen;
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architecture syn of ib_rlim_gen is
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type regs_type is record -- state registers
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cnt : slv7; -- usec counter
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cev : slv8; -- ce vector
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end record regs_type;
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constant regs_init : regs_type := (
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(others=>'0'), -- cnt
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(others=>'0') -- cev
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);
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signal R_REGS : regs_type := regs_init;
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signal N_REGS : regs_type := regs_init;
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begin
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proc_regs: process (CLK)
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begin
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if rising_edge(CLK) then
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if RESET = '1' then
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R_REGS <= regs_init;
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else
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R_REGS <= N_REGS;
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end if;
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end if;
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end process proc_regs;
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proc_next : process (R_REGS, CE_USEC, CPUSUSP)
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variable r : regs_type := regs_init;
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variable n : regs_type := regs_init;
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begin
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r := R_REGS;
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n := R_REGS;
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n.cev := (others=>'0');
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if CPUSUSP = '0' then -- run timers if CPU not suspended
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n.cev(0) := '1'; -- none
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if CE_USEC = '1' then
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n.cev(1) := '1'; -- 1: 1
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n.cnt := slv(unsigned(r.cnt) + 1);
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if r.cnt(0 downto 0) = "1" then n.cev(2) := '1'; end if; -- 1: 2
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if r.cnt(1 downto 0) = "11" then n.cev(3) := '1'; end if; -- 1: 4
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if r.cnt(2 downto 0) = "111" then n.cev(4) := '1'; end if; -- 1: 8
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if r.cnt(4 downto 0) = "11111" then n.cev(5) := '1'; end if; -- 1: 32
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if r.cnt(5 downto 0) = "111111" then n.cev(6) := '1'; end if; -- 1: 64
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if r.cnt(6 downto 0) = "1111111" then n.cev(7) := '1'; end if; -- 1:128
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end if;
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end if;
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N_REGS <= n;
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RLIM_CEV <= r.cev;
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end process proc_next;
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end syn;
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