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82 lines
2.9 KiB
VHDL
82 lines
2.9 KiB
VHDL
-- $Id: ram_1swsr_wfirst_gen.vhd 1181 2019-07-08 17:00:50Z mueller $
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-- SPDX-License-Identifier: GPL-3.0-or-later
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-- Copyright 2006-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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------------------------------------------------------------------------------
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-- Module Name: ram_1swsr_rfirst_gen - syn
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-- Description: Single-Port RAM with with one synchronous read/write port
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-- and 'read-through' semantics (as block RAM).
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-- The 'ram_style' attribute is set to 'block', this will
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-- force in XST a synthesis as block RAM.
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--
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-- Notes: For xst 8.1.03i: can be written with a signal or a shared
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-- variable declared at the architecture level. Use variable
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-- because this seemed better for simulation. Using a simple
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-- variable declared at process level leads to an array of
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-- registers and a big mux.
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--
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-- Dependencies: -
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-- Test bench: -
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-- Target Devices: generic Spartan, Virtex
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-- Tool versions: xst 8.2-14.7; ghdl 0.18-0.31
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-- Revision History:
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-- Date Rev Version Comment
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-- 2011-11-08 422 1.0.4 now numeric_std clean
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-- 2010-06-03 299 1.0.3 use sv_ prefix for shared variables
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-- 2008-03-08 123 1.0.2 use std_..._arith, not _unsigned; use unsigned();
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-- 2008-03-02 122 1.0.1 change generic default for BRAM models
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-- 2007-06-03 45 1.0 Initial version
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.slvtypes.all;
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entity ram_1swsr_wfirst_gen is -- RAM, 1 sync r/w ports, write first
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generic (
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AWIDTH : positive := 11; -- address port width
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DWIDTH : positive := 9); -- data port width
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port(
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CLK : in slbit; -- clock
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EN : in slbit; -- enable
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WE : in slbit; -- write enable
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ADDR : in slv(AWIDTH-1 downto 0); -- address port
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DI : in slv(DWIDTH-1 downto 0); -- data in port
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DO : out slv(DWIDTH-1 downto 0) -- data out port
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);
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end ram_1swsr_wfirst_gen;
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architecture syn of ram_1swsr_wfirst_gen is
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constant memsize : positive := 2**AWIDTH;
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constant datzero : slv(DWIDTH-1 downto 0) := (others=>'0');
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type ram_type is array (0 to memsize-1) of slv(DWIDTH-1 downto 0);
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shared variable sv_ram : ram_type := (others=>datzero);
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attribute ram_style : string;
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attribute ram_style of sv_ram : variable is "block";
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signal R_DO : slv(DWIDTH-1 downto 0) := datzero;
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begin
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proc_clk: process (CLK)
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begin
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if rising_edge(CLK) then
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if EN = '1' then
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if WE = '1' then
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sv_ram(to_integer(unsigned(ADDR))) := DI;
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end if;
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R_DO <= sv_ram(to_integer(unsigned(ADDR)));
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end if;
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end if;
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end process proc_clk;
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DO <= R_DO;
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end syn;
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