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66 lines
2.0 KiB
VHDL
66 lines
2.0 KiB
VHDL
-- $Id: tbd_fifo_simple_dram.vhd 1181 2019-07-08 17:00:50Z mueller $
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-- SPDX-License-Identifier: GPL-3.0-or-later
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-- Copyright 2019- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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------------------------------------------------------------------------------
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-- Module Name: tbd_fifo_simple_dram - syn
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-- Description: Wrapper for fifo_simple_dram to avoid records & generics. It
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-- has a port interface which will not be modified by xst
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-- synthesis (no records, no generic port).
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--
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-- Dependencies: fifo_simple_dram
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--
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-- To test: fifo_simple_dram
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--
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-- Target Devices: generic
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--
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-- Tool versions: xst 14.7; viv 2017.2; ghdl 0.35
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-- Revision History:
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-- Date Rev Version Comment
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-- 2019-02-09 1109 1.0 Initial version
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use work.slvtypes.all;
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use work.memlib.all;
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entity tbd_fifo_simple_dram is -- fifo, CE/WE, dram based [tb design]
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-- generic: AWIDTH=4; DWIDTH=16
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port (
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CLK : in slbit; -- clock
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RESET : in slbit; -- reset
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CE : in slbit; -- clock enable
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WE : in slbit; -- write enable
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DI : in slv16; -- input data
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DO : out slv16; -- output data
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EMPTY : out slbit; -- fifo empty status
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FULL : out slbit; -- fifo full status
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SIZE : out slv4 -- number of used slots
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);
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end tbd_fifo_simple_dram;
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architecture syn of tbd_fifo_simple_dram is
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begin
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FIFO : fifo_simple_dram
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generic map (
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AWIDTH => 4,
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DWIDTH => 16)
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port map (
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CLK => CLK,
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RESET => RESET,
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CE => CE,
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WE => WE,
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DI => DI,
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DO => DO,
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EMPTY => EMPTY,
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FULL => FULL,
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SIZE => SIZE
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);
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end syn;
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