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100 lines
2.5 KiB
VHDL
100 lines
2.5 KiB
VHDL
-- $Id: rbd_usracc.vhd 1181 2019-07-08 17:00:50Z mueller $
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-- SPDX-License-Identifier: GPL-3.0-or-later
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-- Copyright 2016-2018 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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------------------------------------------------------------------------------
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-- Module Name: rbd_usracc - syn
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-- Description: rbus dev: return usr_access register (bitfile+jtag timestamp)
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--
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-- Dependencies: xlib/usr_access_unisim
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-- Test bench: -
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--
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-- Target Devices: generic
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-- Tool versions: viv 2015.4-2018.2; ghdl 0.33-0.34
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--
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-- Revision History:
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-- Date Rev Version Comment
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-- 2016-04-02 758 1.0 Initial version
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------------------------------------------------------------------------------
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--
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-- rbus registers:
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--
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-- Addr Bits Name r/w/f Function
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-- 0 ua0 r/-/- use_accress lsb
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-- 1 ua1 r/-/- use_accress msb
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--
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.slvtypes.all;
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use work.xlib.all;
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use work.rblib.all;
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use work.rbdlib.all;
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entity rbd_usracc is -- rbus dev: return usr_access register
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generic (
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RB_ADDR : slv16 := rbaddr_usracc);
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port (
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CLK : in slbit; -- clock
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RB_MREQ : in rb_mreq_type; -- rbus: request
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RB_SRES : out rb_sres_type -- rbus: response
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);
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end entity rbd_usracc;
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architecture syn of rbd_usracc is
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signal R_SEL : slbit := '0';
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signal DATA : slv32 := (others=>'0');
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begin
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RBSEL : rb_sel
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generic map (
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RB_ADDR => RB_ADDR,
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SAWIDTH => 1)
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port map (
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CLK => CLK,
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RB_MREQ => RB_MREQ,
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SEL => R_SEL
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);
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UA : usr_access_unisim
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port map (DATA => DATA);
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proc_next : process (R_SEL, RB_MREQ, DATA)
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variable irb_ack : slbit := '0';
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variable irb_err : slbit := '0';
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variable irb_dout : slv16 := (others=>'0');
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begin
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irb_ack := '0';
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irb_err := '0';
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irb_dout := (others=>'0');
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-- rbus transactions
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if R_SEL = '1' then
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irb_ack := RB_MREQ.re or RB_MREQ.we;
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if RB_MREQ.we = '1' then
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irb_err := '1';
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end if;
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if RB_MREQ.re = '1' then
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case (RB_MREQ.addr(0)) is
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when '0' => irb_dout := DATA(15 downto 0);
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when '1' => irb_dout := DATA(31 downto 16);
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when others => null;
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end case;
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end if;
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end if;
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RB_SRES.dout <= irb_dout;
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RB_SRES.ack <= irb_ack;
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RB_SRES.err <= irb_err;
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RB_SRES.busy <= '0';
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end process proc_next;
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end syn;
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