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335 lines
12 KiB
Tcl
335 lines
12 KiB
Tcl
# $Id: viv_tools_build.tcl 1242 2022-05-27 17:08:43Z mueller $
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# SPDX-License-Identifier: GPL-3.0-or-later
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# Copyright 2015-2022 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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#
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# Revision History:
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# Date Rev Version Comment
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# 2022-05-26 1242 1.2.5 increase message limit for Synth 8-7129
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# 2018-12-30 1099 1.2.4 downgrade SSN critical warnings to warnings
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# 2018-12-19 1090 1.2.3 export log and rpt generated in OOC synthesis runs
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# 2018-11-18 1072 1.2.2 increase message limits (all 200, some 5000)
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# 2016-09-18 809 1.2.1 keep hierarchy for synthesis only runs
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# 2016-05-22 767 1.2 cleaner setup handling; use explore flows
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# add 2016.1 specific setups
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# 2016-04-02 758 1.1.5 remove USR_ACCESS setup, must be done in xdc
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# 2016-03-26 752 1.1.4 more steps supported: prj,opt,pla
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# 2016-03-25 751 1.1.3 suppress some messages
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# 2016-03-19 748 1.1.2 set bitstream USR_ACCESS to TIMESTAMP
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# 2016-02-28 738 1.1.1 add 2015.4 specific setups
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# 2015-02-21 649 1.1 add 2014.4 specific setups
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# 2015-02-14 646 1.0 Initial version
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#
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#
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# --------------------------------------------------------------------
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#
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proc rvtb_trace_cmd {cmd} {
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puts "# $cmd"
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eval $cmd
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return
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}
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#
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# --------------------------------------------------------------------
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#
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proc rvtb_locate_setup_file {stem} {
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set name "${stem}_setup.tcl"
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if {[file readable $name]} {return $name}
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set name "$../{stem}_setup.tcl"
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if {[file readable $name]} {return $name}
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return
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}
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#
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# --------------------------------------------------------------------
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#
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proc rvtb_mv_file {src dst} {
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if {[file readable $src]} {
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exec mv $src $dst
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} else {
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puts "rvtb_mv_file-W: file '$src' not existing"
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}
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return
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}
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#
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# --------------------------------------------------------------------
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#
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proc rvtb_rm_file {src} {
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exec rm -f $src
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}
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#
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# --------------------------------------------------------------------
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#
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proc rvtb_cp_file {src dst} {
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if {[file readable $src]} {
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exec cp -p $src $dst
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} else {
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puts "rvtb_cp_file-W: file '$src' not existing"
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}
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return
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}
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#
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# --------------------------------------------------------------------
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#
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proc rvtb_build_check {step} {
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return
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}
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#
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# --------------------------------------------------------------------
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#
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proc rvtb_version_is {val} {
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set vers [version -short]
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return [expr {$vers eq $val}]
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}
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#
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# --------------------------------------------------------------------
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#
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proc rvtb_version_min {val} {
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set vers [version -short]
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return [expr {[string compare $vers $val] >= 0}]
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}
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#
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# --------------------------------------------------------------------
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#
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proc rvtb_version_max {val} {
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set vers [version -short]
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return [expr {[string compare $vers $val] <= 0}]
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}
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#
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# --------------------------------------------------------------------
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#
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proc rvtb_version_in {min max} {
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set vers [version -short]
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return [expr {[string compare $vers $min] >= 0 && \
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[string compare $vers $max] <= 0}]
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}
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#
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# --------------------------------------------------------------------
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#
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proc rvtb_default_build {stem step} {
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# supported step values
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# prj setup project
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# syn run synthesis
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# opt run synthesis + implementation up to step opt_design
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# pla run synthesis + implementation up to step place_design
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# imp run synthesis + implementation (but not bit file generation)
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# bit Synthesize + Implement + generate bit file
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if {![regexp -- {^(prj|syn|opt|pla|imp|bit)$} $step]} {
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error "bad step name $step"
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}
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# general setups (prior to project creation) ------------------
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# version dependent setups
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if {[rvtb_version_is "2014.4"]} {
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# suppress nonsense "cannot add Board Part xilinx.com:kc705..." messages
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# set here to avoid messages during create_project
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set_msg_config -suppress -id {Board 49-26}
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}
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# read setup
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set setup_file [rvtb_locate_setup_file $stem]
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if {$setup_file ne ""} {source -notrace $setup_file}
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# Create project ----------------------------------------------
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rvtb_trace_cmd "create_project project_mflow ./project_mflow"
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# Setup project properties -------------------------------
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set obj [get_projects project_mflow]
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set_property "default_lib" "xil_defaultlib" $obj
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set_property "part" $::rvtb_part $obj
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set_property "simulator_language" "Mixed" $obj
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set_property "target_language" "VHDL" $obj
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# general setups -----------------------------------------
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# suppress message which don't convey useful information
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set_msg_config -suppress -id {[DRC 23-20]}; # DSP48 output pilelining
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set_msg_config -suppress -id {[Project 1-120]}; # WebTalk mandatory
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set_msg_config -suppress -id {[Common 17-186]}; # WebTalk info send
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# set message default limit to 200 (buildin default is 100)
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set_param messaging.defaultLimit 200
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# set message limit to 5000 for some cases
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# Synth 8-3331 : design xxx has unconnected port yyy
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# Synth 8-3332 : Sequential element xxx is unused .. removed from yyy
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# Synth 8-7129 : Port xxx in module yyy is either unconnected or no load
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set_msg_config -id {[Synth 8-3331]} -limit 5000
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set_msg_config -id {[Synth 8-3332]} -limit 5000
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set_msg_config -id {[Synth 8-7129]} -limit 5000
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# downgrade 'exceed allowable noise margins' from 'critical' to 'warnings'
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# otherwise some MIG designs will not accepted to generate a bit file
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# see https://www.xilinx.com/support/answers/36141.html
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set_msg_config -id {[Designutils 20-923]} -new_severity {WARNING}
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# Setup list of extra synthesis options (for later rodinMoreOptions)
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set synth_more_opts {}
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# version independent setups -----------------------------
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# setup synthesis strategy and options --------------
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set_property strategy Flow_PerfOptimized_high [get_runs synth_1]
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# for synthesis only: keep hierarchy for easier debug
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if {$step eq "syn"} {
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set_property STEPS.SYNTH_DESIGN.ARGS.FLATTEN_HIERARCHY none \
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[get_runs synth_1]
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}
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# FSM recognition threshold (default is 5)
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# see http://www.xilinx.com/support/answers/58574.html
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lappend synth_more_opts {rt::set_parameter minFsmStates 3}
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# setup implementation strategy and options ---------
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set_property strategy Performance_Explore [get_runs impl_1]
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# version dependent setups -------------------------------
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if {[rvtb_version_is "2014.4"]} {
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# suppress nonsense "cannot add Board Part xilinx.com:kc705..." messages
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# repeated here because create_project apparently clears msg_config
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set_msg_config -suppress -id {Board 49-26}
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}
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if {[rvtb_version_is "2015.4"]} {
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# enable vhdl asserts, see http://www.xilinx.com/support/answers/65415.html
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lappend synth_more_opts {rt::set_parameter ignoreVhdlAssertStmts false}
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}
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if {[rvtb_version_min "2016.1"]} {
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# enable vhdl asserts via global option (after 2016.1)
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set_property STEPS.SYNTH_DESIGN.ARGS.ASSERT true [get_runs synth_1]
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}
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# now setup extra synthesis options
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# see http://www.xilinx.com/support/answers/58248.html
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# -> since used via 'set_param' it's a parameter
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# -> only last definition counts
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# -> use ';' separated list
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# -> these options are **NOT** preserved in project file !!
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if {[llength $synth_more_opts]} {
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puts "# extra synthesis options:"
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foreach opt $synth_more_opts { puts "# $opt"}
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set_param synth.elaboration.rodinMoreOptions [join $synth_more_opts "; "]
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}
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# Setup filesets
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set vbom_prj [exec vbomconv -vsyn_prj "${stem}.vbom"]
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eval $vbom_prj
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update_compile_order -fileset sources_1
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if {$step eq "prj"} {
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puts "rvtb_default_build-I: new project setup for ${stem}"
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return
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}
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# some handy variables
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set path_runs "project_mflow/project_mflow.runs"
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set path_syn1 "${path_runs}/synth_1"
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set path_imp1 "${path_runs}/impl_1"
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# build: synthesize ------------------------------------------------
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puts "# current rodinMoreOptions:"
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puts [get_param synth.elaboration.rodinMoreOptions]
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rvtb_trace_cmd "launch_runs synth_1"
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rvtb_trace_cmd "wait_on_run synth_1"
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rvtb_mv_file "$path_syn1/runme.log" "${stem}_syn.log"
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rvtb_cp_file "$path_syn1/${stem}_utilization_synth.rpt" "${stem}_syn_util.rpt"
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rvtb_cp_file "$path_syn1/${stem}.dcp" "${stem}_syn.dcp"
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# export log and syn_util generated in OOC synthesis runs
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set ooc_dirs [glob -nocomplain -dir $path_runs -tails -type d "*_synth_1"]
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foreach ooc_dir $ooc_dirs {
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puts "# process OOC build $ooc_dir"
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set ooc_core [regsub -- {_synth_1$} $ooc_dir {}]
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rvtb_cp_file \
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"${path_runs}/${ooc_dir}/runme.log" \
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"${stem}_${ooc_core}_syn.log"
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rvtb_cp_file \
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"${path_runs}/${ooc_dir}/${ooc_core}_utilization_synth.rpt" \
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"${stem}_${ooc_core}_syn_util.rpt"
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}
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if {$step eq "syn"} {return [rvtb_build_check $step]}
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# build: implement -------------------------------------------------
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set launch_opt ""
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if {$step eq "opt"} {set launch_opt "-to_step opt_design"}
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if {$step eq "pla"} {set launch_opt "-to_step place_design"}
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rvtb_trace_cmd "launch_runs ${launch_opt} impl_1"
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rvtb_trace_cmd "wait_on_run impl_1"
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rvtb_cp_file "$path_imp1/runme.log" "${stem}_imp.log"
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rvtb_cp_file "$path_imp1/${stem}_opt.dcp" "${stem}_opt.dcp"
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rvtb_cp_file "$path_imp1/${stem}_drc_opted.rpt" "${stem}_opt_drc.rpt"
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if {$step eq "opt"} {
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rvtb_trace_cmd "open_checkpoint $path_imp1/${stem}_opt.dcp"
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report_utilization -file "${stem}_opt_util.rpt"
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report_utilization -hierarchical -file "${stem}_opt_util_h.rpt"
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return [rvtb_build_check $step]
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}
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rvtb_cp_file "$path_imp1/${stem}_placed.dcp" "${stem}_pla.dcp"
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rvtb_cp_file "$path_imp1/${stem}_io_placed.rpt" "${stem}_pla_io.rpt"
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rvtb_cp_file "$path_imp1/${stem}_utilization_placed.rpt" \
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"${stem}_pla_util.rpt"
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rvtb_cp_file "$path_imp1/${stem}_control_sets_placed.rpt" \
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"${stem}_pla_clk_set.rpt"
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if {$step eq "pla"} {
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return [rvtb_build_check $step]
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}
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rvtb_cp_file "$path_imp1/${stem}_routed.dcp" "${stem}_rou.dcp"
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rvtb_cp_file "$path_imp1/${stem}_route_status.rpt" "${stem}_rou_sta.rpt"
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rvtb_cp_file "$path_imp1/${stem}_drc_routed.rpt" "${stem}_rou_drc.rpt"
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rvtb_cp_file "$path_imp1/${stem}_timing_summary_routed.rpt" \
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"${stem}_rou_tim.rpt"
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rvtb_cp_file "$path_imp1/${stem}_power_routed.rpt" "${stem}_rou_pwr.rpt"
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rvtb_cp_file "$path_imp1/${stem}_clock_utilization_routed.rpt" \
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"${stem}_rou_clk_util.rpt"
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# additional reports
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rvtb_trace_cmd "open_run impl_1"
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report_utilization -file "${stem}_rou_util.rpt"
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report_utilization -hierarchical -file "${stem}_rou_util_h.rpt"
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report_datasheet -file "${stem}_rou_ds.rpt"
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report_cdc -file "${stem}_rou_cdc.rpt"
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report_clock_interaction -delay_type min_max -significant_digits 3 \
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-file "${stem}_rou_clk_int.rpt"
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if {[get_property SSN_REPORT [get_property PART [current_project]]]} {
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report_ssn -format TXT -file "${stem}_rou_ssn.rpt"
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}
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if {$step eq "imp"} {return [rvtb_build_check $step]}
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# build: bitstream -------------------------------------------------
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# check for critical warnings, e.g.
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# [Timing 38-282] The design failed to meet the timing requirements.
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# in that case abort build
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rvtb_rm_file "./${stem}.bit"
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if {[get_msg_config -severity {critical warning} -count]} {
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puts "rvtb_default_build-E: abort due to critical warnings seen before"
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puts "rvtb_default_build-E: no bitfile generated"
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return [rvtb_build_check $step]
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}
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rvtb_trace_cmd "launch_runs impl_1 -to_step write_bitstream"
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rvtb_trace_cmd "wait_on_run impl_1"
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rvtb_mv_file "$path_imp1/runme.log" "${stem}_bit.log"
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rvtb_mv_file "$path_imp1/${stem}.bit" "."
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return [rvtb_build_check $step]
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}
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