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0c395856d7
- add fifo_simple_dram: simple fifo with CE/WE interface, dram based - add test benches for fifo_simple_dram, fifo_2c_dram, and fifo_2c_dram2 - add simclkv: test bench clock generator with variable period
9 lines
158 B
Plaintext
9 lines
158 B
Plaintext
tb_fifo_1c_dram
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tb_fifo_1c_dram_stim
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tb_fifo_2c_dram
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tb_fifo_2c_dram_stim
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tb_fifo_2c_dram2
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tb_fifo_2c_dram2_stim
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tb_fifo_simple_dram
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tb_fifo_simple_dram_stim
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