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382 lines
17 KiB
VHDL
382 lines
17 KiB
VHDL
-- $Id: ibdlib.vhd 1181 2019-07-08 17:00:50Z mueller $
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-- SPDX-License-Identifier: GPL-3.0-or-later
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-- Copyright 2008-2019 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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------------------------------------------------------------------------------
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-- Package Name: ibdlib
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-- Description: Definitions for ibus devices
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--
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-- Dependencies: -
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-- Tool versions: ise 8.2-14.7; viv 2014.4-2018.3; ghdl 0.18-0.35
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-- Revision History:
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-- Date Rev Version Comment
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-- 2019-04-28 1142 1.3.8 add ibd_m9312
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-- 2019-04-26 1139 1.3.7 add ibdr_dl11_buf
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-- 2019-04-14 1131 1.3.6 RLIM_CEV now slv8
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-- 2019-04-07 1129 1.3.5 add ibdr_pc11_buf
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-- 2019-04-07 1128 1.3.4 ibdr_dl11: use RLIM_CEV, drop CE_USEC
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-- 2019-03-09 1121 1.3.3 add ibdr_lp11_buf
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-- 2018-10-13 1055 1.3.2 update ibdr_maxisys (add IDEC port)
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-- 2018-09-08 1043 1.3.1 update ibd_kw11p
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-- 2017-01-29 847 1.3.1 add ibdr_deuna
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-- 2015-05-09 676 1.3 start/stop/suspend overhaul
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-- 2015-03-13 658 1.2.1 add rprm declaration (later renaned to rhrp)
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-- 2014-06-08 561 1.2 fix rl11 declaration
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-- 2011-11-18 427 1.1.2 now numeric_std clean
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-- 2010-10-23 335 1.1.1 rename RRI_LAM->RB_LAM;
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-- 2010-06-11 303 1.1 use IB_MREQ.racc instead of RRI_REQ
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-- 2009-07-12 233 1.0.5 add RESET, CE_USEC to _dl11, CE_USEC to _minisys
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-- 2009-06-07 224 1.0.4 add iist_mreq and iist_sreq;
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-- 2009-06-01 221 1.0.3 add RESET to kw11l; add iist;
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-- 2009-05-30 220 1.0.2 add most additional device def's
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-- 2009-05-24 219 1.0.1 add CE_MSEC to _rk11; add _maxisys
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-- 2008-08-22 161 1.0 Initial version (extracted from pdp11.vhd)
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.slvtypes.all;
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use work.iblib.all;
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package ibdlib is
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type iist_line_type is record -- iist line
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dcf : slbit; -- disconnect flag
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req : slbit; -- request
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stf : slbit; -- sanity timer flag
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imask : slv4; -- interrupt mask
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bmask : slv4; -- boot mask
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par : slbit; -- parity (odd)
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frm : slbit; -- frame error flag
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end record iist_line_type;
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constant iist_line_init : iist_line_type := ('1','0','0',"0000","0000",'0','0');
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type iist_bus_type is array (3 downto 0) of iist_line_type;
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constant iist_bus_init : iist_bus_type := (others=>iist_line_init);
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type iist_mreq_type is record -- iist->cpu requests
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lock : slbit; -- lock-up CPU
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boot : slbit; -- boot-up CPU
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end record iist_mreq_type;
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constant iist_mreq_init : iist_mreq_type := ('0','0');
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type iist_sres_type is record -- cpu->iist responses
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ack_lock : slbit; -- release lock
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ack_boot : slbit; -- boot started
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end record iist_sres_type;
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constant iist_sres_init : iist_sres_type := ('0','0');
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-- ise 13.1 xst can bug check if generic defaults in a package are defined via
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-- 'slv(to_unsigned())'. The conv_ construct prior to numeric_std was ok.
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-- As workaround the ibus default addresses are defined here as constant.
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constant ibaddr_dz11 : slv16 := slv(to_unsigned(8#160100#,16));
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constant ibaddr_dl11 : slv16 := slv(to_unsigned(8#177560#,16));
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component ibd_iist is -- ibus dev(loc): IIST
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-- fixed address: 177500
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generic (
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SID : slv2 := "00"); -- self id
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port (
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CLK : in slbit; -- clock
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CE_USEC : in slbit; -- usec pulse
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RESET : in slbit; -- system reset
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BRESET : in slbit; -- ibus reset
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IB_MREQ : in ib_mreq_type; -- ibus request
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IB_SRES : out ib_sres_type; -- ibus response
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EI_REQ : out slbit; -- interrupt request
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EI_ACK : in slbit; -- interrupt acknowledge
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IIST_BUS : in iist_bus_type; -- iist bus (input from all iist's)
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IIST_OUT : out iist_line_type; -- iist output
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IIST_MREQ : out iist_mreq_type; -- iist->cpu requests
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IIST_SRES : in iist_sres_type -- cpu->iist responses
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);
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end component;
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component ibd_kw11p is -- ibus dev(loc): KW11-P (prog clock)
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-- fixed address: 172540
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port (
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CLK : in slbit; -- clock
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CE_USEC : in slbit; -- usec pulse
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CE_MSEC : in slbit; -- msec pulse
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RESET : in slbit; -- system reset
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BRESET : in slbit; -- ibus reset
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EXTEVT : in slbit; -- external event for RATE="11"
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CPUSUSP : in slbit; -- cpu suspended
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IB_MREQ : in ib_mreq_type; -- ibus request
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IB_SRES : out ib_sres_type; -- ibus response
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EI_REQ : out slbit; -- interrupt request
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EI_ACK : in slbit -- interrupt acknowledge
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);
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end component;
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component ibd_kw11l is -- ibus dev(loc): KW11-L (line clock)
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-- fixed address: 177546
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port (
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CLK : in slbit; -- clock
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CE_MSEC : in slbit; -- msec pulse
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RESET : in slbit; -- system reset
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BRESET : in slbit; -- ibus reset
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CPUSUSP : in slbit; -- cpu suspended
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IB_MREQ : in ib_mreq_type; -- ibus request
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IB_SRES : out ib_sres_type; -- ibus response
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EI_REQ : out slbit; -- interrupt request
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EI_ACK : in slbit -- interrupt acknowledge
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);
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end component;
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component ibdr_deuna is -- ibus dev(rem): DEUNA
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-- fixed address: 174510
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port (
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CLK : in slbit; -- clock
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BRESET : in slbit; -- ibus reset
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RB_LAM : out slbit; -- remote attention
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IB_MREQ : in ib_mreq_type; -- ibus request
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IB_SRES : out ib_sres_type; -- ibus response
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EI_REQ : out slbit; -- interrupt request
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EI_ACK : in slbit -- interrupt acknowledge
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);
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end component;
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component ibdr_rhrp is -- ibus dev(rem): RH+RP
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-- fixed address: 174400
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port (
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CLK : in slbit; -- clock
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CE_USEC : in slbit; -- usec pulse
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BRESET : in slbit; -- ibus reset
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ITIMER : in slbit; -- instruction timer
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RB_LAM : out slbit; -- remote attention
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IB_MREQ : in ib_mreq_type; -- ibus request
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IB_SRES : out ib_sres_type; -- ibus response
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EI_REQ : out slbit; -- interrupt request
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EI_ACK : in slbit -- interrupt acknowledge
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);
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end component;
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component ibdr_rl11 is -- ibus dev(rem): RL11
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-- fixed address: 174400
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port (
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CLK : in slbit; -- clock
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CE_MSEC : in slbit; -- msec pulse
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BRESET : in slbit; -- ibus reset
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RB_LAM : out slbit; -- remote attention
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IB_MREQ : in ib_mreq_type; -- ibus request
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IB_SRES : out ib_sres_type; -- ibus response
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EI_REQ : out slbit; -- interrupt request
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EI_ACK : in slbit -- interrupt acknowledge
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);
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end component;
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component ibdr_rk11 is -- ibus dev(rem): RK11
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-- fixed address: 177400
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port (
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CLK : in slbit; -- clock
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CE_MSEC : in slbit; -- msec pulse
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BRESET : in slbit; -- ibus reset
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RB_LAM : out slbit; -- remote attention
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IB_MREQ : in ib_mreq_type; -- ibus request
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IB_SRES : out ib_sres_type; -- ibus response
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EI_REQ : out slbit; -- interrupt request
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EI_ACK : in slbit -- interrupt acknowledge
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);
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end component;
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component ibdr_tm11 is -- ibus dev(rem): TM11
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-- fixed address: 172520
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port (
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CLK : in slbit; -- clock
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BRESET : in slbit; -- ibus reset
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RB_LAM : out slbit; -- remote attention
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IB_MREQ : in ib_mreq_type; -- ibus request
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IB_SRES : out ib_sres_type; -- ibus response
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EI_REQ : out slbit; -- interrupt request
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EI_ACK : in slbit -- interrupt acknowledge
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);
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end component;
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component ibdr_dz11 is -- ibus dev(rem): DZ11
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generic (
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IB_ADDR : slv16 := ibaddr_dz11;
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AWIDTH : natural := 5); -- fifo address width
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port (
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CLK : in slbit; -- clock
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RESET : in slbit; -- system reset
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BRESET : in slbit; -- ibus reset
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RLIM_CEV : in slv8; -- clock enable vector
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RB_LAM : out slbit; -- remote attention
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IB_MREQ : in ib_mreq_type; -- ibus request
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IB_SRES : out ib_sres_type; -- ibus response
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EI_REQ_RX : out slbit; -- interrupt request, receiver
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EI_REQ_TX : out slbit; -- interrupt request, transmitter
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EI_ACK_RX : in slbit; -- interrupt acknowledge, receiver
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EI_ACK_TX : in slbit -- interrupt acknowledge, transmitter
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);
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end component;
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component ibdr_dl11 is -- ibus dev(rem): DL11-A/B
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generic (
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IB_ADDR : slv16 := ibaddr_dl11);
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port (
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CLK : in slbit; -- clock
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RESET : in slbit; -- system reset
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BRESET : in slbit; -- ibus reset
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RLIM_CEV : in slv8; -- clock enable vector
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RB_LAM : out slbit; -- remote attention
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IB_MREQ : in ib_mreq_type; -- ibus request
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IB_SRES : out ib_sres_type; -- ibus response
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EI_REQ_RX : out slbit; -- interrupt request, receiver
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EI_REQ_TX : out slbit; -- interrupt request, transmitter
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EI_ACK_RX : in slbit; -- interrupt acknowledge, receiver
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EI_ACK_TX : in slbit -- interrupt acknowledge, transmitter
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);
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end component;
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component ibdr_dl11_buf is -- ibus dev(rem): DL11-A/B
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generic (
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IB_ADDR : slv16 := ibaddr_dl11;
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AWIDTH : natural := 5); -- fifo address width
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port (
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CLK : in slbit; -- clock
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RESET : in slbit; -- system reset
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BRESET : in slbit; -- ibus reset
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RLIM_CEV : in slv8; -- clock enable vector
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RB_LAM : out slbit; -- remote attention
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IB_MREQ : in ib_mreq_type; -- ibus request
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IB_SRES : out ib_sres_type; -- ibus response
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EI_REQ_RX : out slbit; -- interrupt request, receiver
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EI_REQ_TX : out slbit; -- interrupt request, transmitter
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EI_ACK_RX : in slbit; -- interrupt acknowledge, receiver
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EI_ACK_TX : in slbit -- interrupt acknowledge, transmitter
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);
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end component;
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component ibdr_pc11 is -- ibus dev(rem): PC11
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-- fixed address: 177550
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port (
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CLK : in slbit; -- clock
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RESET : in slbit; -- system reset
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BRESET : in slbit; -- ibus reset
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RB_LAM : out slbit; -- remote attention
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IB_MREQ : in ib_mreq_type; -- ibus request
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IB_SRES : out ib_sres_type; -- ibus response
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EI_REQ_PTR : out slbit; -- interrupt request, reader
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EI_REQ_PTP : out slbit; -- interrupt request, punch
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EI_ACK_PTR : in slbit; -- interrupt acknowledge, reader
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EI_ACK_PTP : in slbit -- interrupt acknowledge, punch
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);
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end component;
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component ibdr_pc11_buf is -- ibus dev(rem): PC11 (buffered)
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-- fixed address: 177550
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generic (
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AWIDTH : natural := 5); -- fifo address width
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port (
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CLK : in slbit; -- clock
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RESET : in slbit; -- system reset
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BRESET : in slbit; -- ibus reset
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RLIM_CEV : in slv8; -- clock enable vector
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RB_LAM : out slbit; -- remote attention
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IB_MREQ : in ib_mreq_type; -- ibus request
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IB_SRES : out ib_sres_type; -- ibus response
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EI_REQ_PTR : out slbit; -- interrupt request, reader
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EI_REQ_PTP : out slbit; -- interrupt request, punch
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EI_ACK_PTR : in slbit; -- interrupt acknowledge, reader
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EI_ACK_PTP : in slbit -- interrupt acknowledge, punch
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);
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end component;
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component ibdr_lp11 is -- ibus dev(rem): LP11
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-- fixed address: 177514
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port (
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CLK : in slbit; -- clock
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RESET : in slbit; -- system reset
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BRESET : in slbit; -- ibus reset
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RB_LAM : out slbit; -- remote attention
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IB_MREQ : in ib_mreq_type; -- ibus request
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IB_SRES : out ib_sres_type; -- ibus response
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EI_REQ : out slbit; -- interrupt request
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EI_ACK : in slbit -- interrupt acknowledge
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);
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end component;
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component ibdr_lp11_buf is -- ibus dev(rem): LP11 (buffered)
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-- fixed address: 177514
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generic (
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AWIDTH : natural := 5); -- fifo address width
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port (
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CLK : in slbit; -- clock
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RESET : in slbit; -- system reset
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BRESET : in slbit; -- ibus reset
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RLIM_CEV : in slv8; -- clock enable vector
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RB_LAM : out slbit; -- remote attention
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IB_MREQ : in ib_mreq_type; -- ibus request
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IB_SRES : out ib_sres_type; -- ibus response
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EI_REQ : out slbit; -- interrupt request
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EI_ACK : in slbit -- interrupt acknowledge
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);
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end component;
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component ibd_m9312 is -- ibus dev: M9312
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-- fixed address: 165***,173***
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port (
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CLK : in slbit; -- clock
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RESET : in slbit; -- system reset
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IB_MREQ : in ib_mreq_type; -- ibus request
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IB_SRES : out ib_sres_type -- ibus response
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);
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end component;
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component ibdr_sdreg is -- ibus dev(rem): Switch/Display regs
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-- fixed address: 177570
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port (
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CLK : in slbit; -- clock
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RESET : in slbit; -- reset
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IB_MREQ : in ib_mreq_type; -- ibus request
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IB_SRES : out ib_sres_type; -- ibus response
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DISPREG : out slv16 -- display register
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);
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end component;
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component ibdr_minisys is -- ibus(rem) minimal sys:SDR+KW+DL+RK
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port (
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CLK : in slbit; -- clock
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CE_USEC : in slbit; -- usec pulse
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CE_MSEC : in slbit; -- msec pulse
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RESET : in slbit; -- reset
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BRESET : in slbit; -- ibus reset
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RB_LAM : out slv16_1; -- remote attention vector
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IB_MREQ : in ib_mreq_type; -- ibus request
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IB_SRES : out ib_sres_type; -- ibus response
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EI_ACKM : in slbit; -- interrupt acknowledge (from master)
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EI_PRI : out slv3; -- interrupt priority (to cpu)
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EI_VECT : out slv9_2; -- interrupt vector (to cpu)
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DISPREG : out slv16 -- display register
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);
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end component;
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component ibdr_maxisys is -- ibus(rem) full system
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port (
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CLK : in slbit; -- clock
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CE_USEC : in slbit; -- usec pulse
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CE_MSEC : in slbit; -- msec pulse
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RESET : in slbit; -- reset
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BRESET : in slbit; -- ibus reset
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ITIMER : in slbit; -- instruction timer
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IDEC : in slbit; -- instruction decode
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CPUSUSP : in slbit; -- cpu suspended
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RB_LAM : out slv16_1; -- remote attention vector
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IB_MREQ : in ib_mreq_type; -- ibus request
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IB_SRES : out ib_sres_type; -- ibus response
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EI_ACKM : in slbit; -- interrupt acknowledge (from master)
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EI_PRI : out slv3; -- interrupt priority (to cpu)
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EI_VECT : out slv9_2; -- interrupt vector (to cpu)
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DISPREG : out slv16 -- display register
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);
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end component;
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end package ibdlib;
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