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213 lines
8.5 KiB
VHDL
213 lines
8.5 KiB
VHDL
-- $Id: iblib.vhd 1181 2019-07-08 17:00:50Z mueller $
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-- SPDX-License-Identifier: GPL-3.0-or-later
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-- Copyright 2008-2019 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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------------------------------------------------------------------------------
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-- Package Name: iblib
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-- Description: Definitions for ibus interface and bus entities
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--
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-- Dependencies: -
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-- Tool versions: ise 8.1-14.7; viv 2014.4-2018.3; ghdl 0.18-0.35
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-- Revision History:
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-- Date Rev Version Comment
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-- 2019-04-23 1136 2.2.4 add CLK port to ib_intmap,ib_intmap24
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-- 2019-04-14 1131 2.2.3 ib_rlim_gen: add CPUSUSP port; RLIM_CEV now slv8
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-- 2019-03-17 1123 2.2.2 add ib_rlim_gen,ib_rlim_slv
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-- 2019-02-10 1111 2.2.1 add ibd_ibtst
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-- 2017-01-28 846 2.2 add ib_intmap24
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-- 2016-05-28 770 2.1.1 use type natural for vec,pri fields of intmap_type
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-- 2015-04-24 668 2.1 add ibd_ibmon
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-- 2010-10-23 335 2.0.1 add ib_sel; add ib_sres_or_mon
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-- 2010-10-17 333 2.0 ibus V2 interface: use aval,re,we,rmw
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-- 2010-06-11 303 1.1 added racc,cacc signals to ib_mreq_type
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-- 2009-06-01 221 1.0.1 added dip signal to ib_mreq_type
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-- 2008-08-22 161 1.0 Initial version (extracted from pdp11.vhd)
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.slvtypes.all;
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package iblib is
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type ib_mreq_type is record -- ibus - master request
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aval : slbit; -- address valid
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re : slbit; -- read enable
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we : slbit; -- write enable
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rmw : slbit; -- read-modify-write
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be0 : slbit; -- byte enable low
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be1 : slbit; -- byte enable high
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cacc : slbit; -- console access
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racc : slbit; -- remote access
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addr : slv13_1; -- address bit(12:1)
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din : slv16; -- data (input to slave)
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end record ib_mreq_type;
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constant ib_mreq_init : ib_mreq_type :=
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('0','0','0','0', -- aval, re, we, rmw
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'0','0','0','0', -- be0, be1, cacc, racc
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(others=>'0'), -- addr
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(others=>'0')); -- din
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type ib_sres_type is record -- ibus - slave response
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ack : slbit; -- acknowledge
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busy : slbit; -- busy
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dout : slv16; -- data (output from slave)
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end record ib_sres_type;
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constant ib_sres_init : ib_sres_type :=
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('0','0', -- ack, busy
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(others=>'0')); -- dout
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type ib_sres_vector is array (natural range <>) of ib_sres_type;
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subtype ibf_byte1 is integer range 15 downto 8;
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subtype ibf_byte0 is integer range 7 downto 0;
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component ib_sel is -- ibus address select logic
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generic (
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IB_ADDR : slv16; -- ibus address base
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SAWIDTH : natural := 0); -- device subaddress space width
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port (
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CLK : in slbit; -- clock
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IB_MREQ : in ib_mreq_type; -- ibus request
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SEL : out slbit -- select state bit
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);
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end component;
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component ib_sres_or_2 is -- ibus result or, 2 input
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port (
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IB_SRES_1 : in ib_sres_type; -- ib_sres input 1
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IB_SRES_2 : in ib_sres_type := ib_sres_init; -- ib_sres input 2
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IB_SRES_OR : out ib_sres_type -- ib_sres or'ed output
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);
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end component;
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component ib_sres_or_3 is -- ibus result or, 3 input
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port (
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IB_SRES_1 : in ib_sres_type; -- ib_sres input 1
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IB_SRES_2 : in ib_sres_type := ib_sres_init; -- ib_sres input 2
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IB_SRES_3 : in ib_sres_type := ib_sres_init; -- ib_sres input 3
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IB_SRES_OR : out ib_sres_type -- ib_sres or'ed output
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);
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end component;
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component ib_sres_or_4 is -- ibus result or, 4 input
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port (
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IB_SRES_1 : in ib_sres_type; -- ib_sres input 1
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IB_SRES_2 : in ib_sres_type := ib_sres_init; -- ib_sres input 2
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IB_SRES_3 : in ib_sres_type := ib_sres_init; -- ib_sres input 3
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IB_SRES_4 : in ib_sres_type := ib_sres_init; -- ib_sres input 4
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IB_SRES_OR : out ib_sres_type -- ib_sres or'ed output
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);
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end component;
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component ib_sres_or_gen is -- ibus result or, generic
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generic (
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WIDTH : natural := 4); -- number of input ports
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port (
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IB_SRES_IN : in ib_sres_vector(1 to WIDTH); -- ib_sres input array
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IB_SRES_OR : out ib_sres_type -- ib_sres or'ed output
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);
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end component;
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type intmap_type is record -- interrupt map entry type
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vec : natural; -- vector address
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pri : natural; -- priority
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end record intmap_type;
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constant intmap_init : intmap_type := (0,0);
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type intmap_array_type is array (15 downto 0) of intmap_type;
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constant intmap_array_init : intmap_array_type := (others=>intmap_init);
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component ib_intmap is -- external interrupt mapper (15 line)
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generic (
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INTMAP : intmap_array_type := intmap_array_init);
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port (
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CLK : in slbit; -- clock
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EI_REQ : in slv16_1; -- interrupt request lines
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EI_ACKM : in slbit; -- interrupt acknowledge (from master)
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EI_ACK : out slv16_1; -- interrupt acknowledge (to requestor)
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EI_PRI : out slv3; -- interrupt priority
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EI_VECT : out slv9_2 -- interrupt vector
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);
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end component;
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type intmap24_array_type is array (23 downto 0) of intmap_type;
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constant intmap24_array_init : intmap24_array_type := (others=>intmap_init);
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component ib_intmap24 is -- external interrupt mapper (23 line)
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generic (
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INTMAP : intmap24_array_type := intmap24_array_init);
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port (
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CLK : in slbit; -- clock
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EI_REQ : in slv24_1; -- interrupt request lines
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EI_ACKM : in slbit; -- interrupt acknowledge (from master)
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EI_ACK : out slv24_1; -- interrupt acknowledge (to requestor)
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EI_PRI : out slv3; -- interrupt priority
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EI_VECT : out slv9_2 -- interrupt vector
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);
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end component;
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component ibd_ibmon is -- ibus dev: ibus monitor
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generic (
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IB_ADDR : slv16 := slv(to_unsigned(8#160000#,16));
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AWIDTH : natural := 9);
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port (
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CLK : in slbit; -- clock
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RESET : in slbit; -- reset
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IB_MREQ : in ib_mreq_type; -- ibus: request
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IB_SRES : out ib_sres_type; -- ibus: response
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IB_SRES_SUM : in ib_sres_type -- ibus: response (sum for monitor)
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);
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end component;
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component ibd_ibtst is -- ibus dev(rem): ibus tester
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generic (
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IB_ADDR : slv16 := slv(to_unsigned(8#170000#,16)));
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port (
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CLK : in slbit; -- clock
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RESET : in slbit; -- reset
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IB_MREQ : in ib_mreq_type; -- ibus request
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IB_SRES : out ib_sres_type -- ibus response
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);
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end component;
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component ib_rlim_gen is -- ibus rate limter - master
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port (
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CLK : in slbit; -- clock
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CE_USEC : in slbit; -- usec pulse
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RESET : in slbit; -- system reset
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CPUSUSP : in slbit; -- cpu suspended
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RLIM_CEV : out slv8 -- clock enable vector
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);
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end component;
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component ib_rlim_slv is -- ibus rate limter - slave
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port (
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CLK : in slbit; -- clock
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RESET : in slbit; -- system reset
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RLIM_CEV : in slv8; -- clock enable vector
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SEL : in slv3; -- rlim select
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START : in slbit; -- start timer
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STOP : in slbit; -- stop timer
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DONE : out slbit; -- 1 cycle pulse when expired
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BUSY : out slbit -- timer running
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);
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end component;
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--
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-- components for use in test benches (not synthesizable)
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--
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component ib_sres_or_mon is -- ibus result or monitor
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port (
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IB_SRES_1 : in ib_sres_type; -- ib_sres input 1
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IB_SRES_2 : in ib_sres_type := ib_sres_init; -- ib_sres input 2
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IB_SRES_3 : in ib_sres_type := ib_sres_init; -- ib_sres input 3
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IB_SRES_4 : in ib_sres_type := ib_sres_init -- ib_sres input 4
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);
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end component;
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end package iblib;
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