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https://github.com/wfjm/w11.git
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360 lines
8.1 KiB
Tcl
360 lines
8.1 KiB
Tcl
# $Id: test_pcnt_codes.tcl 1053 2018-10-06 20:34:52Z mueller $
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#
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# Copyright 2018- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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# License disclaimer see License.txt in $RETROBASE directory
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#
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# Revision History:
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# Date Rev Version Comment
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# 2018-10-06 1053 1.0 Initial version
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#
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# Test perf counter functionality with test codes
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# ----------------------------------------------------------------------------
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rlc log "test_pcnt_codes: test counters --------------------------------------"
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if {[$cpu get haspcnt] == 0} {
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rlc log " test_pcnt_regs-W: no pcnt unit found, test aborted"
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return
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}
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# define tmpproc for execute test
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proc tmpproc_dotest {cpu code args} {
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# compile and load code
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$cpu cp -creset
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$cpu ldasm -lst lst -sym sym $code
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# clear and start dmpcnt
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$cpu cp \
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-wreg pc.cntl [regbld rw11::PC_CNTL {func "CLR"}] \
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-wreg pc.cntl [regbld rw11::PC_CNTL {func "STA"}]
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# run code
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rw11::asmrun $cpu sym
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rw11::asmwait $cpu sym
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# determine pcnt index range to read
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set imin 31
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set imax 0
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foreach {nam val} $args {
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if {! [info exists rw11::pcnt_cindex($nam)]} {
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rlc log "FAIL: invalid counter name '$nam'"
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rlc errcnt -inc
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return
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}
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set i $rw11::pcnt_cindex($nam)
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set imin [expr {min($imin,$i)}]
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set imax [expr {max($imax,$i)}]
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}
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set nwrd [expr {2*($imax-$imin+1)}]
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if {$nwrd <= 0} {
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rlc log "FAIL: no counters to inspect"
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rlc errcnt -inc
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return
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}
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# stop dmpcnt and read counters
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$cpu cp \
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-wreg pc.cntl [regbld rw11::PC_CNTL {func "STO"}] \
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-wreg pc.cntl [regbldkv rw11::PC_CNTL func "LOA" caddr $imin ainc 1] \
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-rreg pc.stat -edata [regbldkv rw11::PC_STAT caddr $imin waddr 0 ainc 1] \
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-rblk pc.data $nwrd pcnt
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## puts [rw11::pc_printraw]
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# inspect counters
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foreach {nam exp} $args {
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set i0 [expr {2*($rw11::pcnt_cindex($nam)-$imin)}]
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set i1 [expr {$i0+1}]
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set v [expr {[lindex $pcnt $i0] + 65536.*[lindex $pcnt $i1]}]
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if {$exp >= 0} {
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if {$v != $exp} {
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rlc log -bare \
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[format "FAIL: $nam expect == $exp, found %1.0f" $v]
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rlc errcnt -inc
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}
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} else {
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if {$v <= -$exp} {
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rlc log -bare \
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[format "FAIL: $nam expect >= %d, found %1.0f" [expr {-$exp}] $v]
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rlc errcnt -inc
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}
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}
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}
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}
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# -- Section A ---------------------------------------------------------------
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rlc log " A: plain kernel mode codes---------------------------------"
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rlc log " A1: plain sob loop ---------------------------------"
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set code {
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. = 1000
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stack:
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start: mov #32.,r0
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1$: sob r0,1$
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halt
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stop:
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}
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# cpu_idec: 34 = 32(sob) + 2(mov+halt)
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# ca_rd: 35 = 2(mov) + 32(sob) + 1(halt)
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tmpproc_dotest $cpu $code \
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cpu_km_prix 0 \
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cpu_km_pri0 -1 \
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cpu_km_wait 0 \
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cpu_sm 0 \
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cpu_um 0 \
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cpu_idec 34 \
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cpu_vfetch 0 \
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cpu_irupt 0 \
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cpu_pcload 31 \
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ca_rd 35 \
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ca_wr 0 \
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ca_rdhit 35 \
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ca_wrhit 0 \
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ca_rdmem 0 \
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ca_wrmem 0
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rlc log " A2: sob + inc R loop -------------------------------"
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set code {
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. = 1000
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stack:
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start: mov #32.,r0
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clr r1
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1$: inc r1
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sob r0,1$
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halt
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stop:
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}
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# cpu_idec: 67 = 64(inc+sob) + 2(mov+clr+halt)
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# ca_rd: 68 = 3(mov+clr) + 64(inc+sob) + 1(halt)
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tmpproc_dotest $cpu $code \
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cpu_km_prix 0 \
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cpu_km_pri0 -1 \
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cpu_km_wait 0 \
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cpu_sm 0 \
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cpu_um 0 \
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cpu_idec 67 \
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cpu_pcload 31 \
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cpu_vfetch 0 \
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cpu_irupt 0 \
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ca_rd 68 \
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ca_wr 0 \
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ca_rdhit 68 \
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ca_wrhit 0 \
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ca_rdmem 0 \
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ca_wrmem 0
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rlc log " A3: sob + inc mem loop -----------------------------"
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set code {
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. = 1000
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stack:
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start: mov #32.,r0
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clr cnt
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1$: inc cnt
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sob r0,1$
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halt
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stop:
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cnt: .word 0
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}
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# cpu_idec: 67 = 64(inc+sob) + 2(mov+clr+halt)
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# ca_rd: 133 = 4(mov+clr) + 128(inc+sob) + 1(halt)
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tmpproc_dotest $cpu $code \
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cpu_km_prix 0 \
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cpu_km_pri0 -1 \
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cpu_km_wait 0 \
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cpu_sm 0 \
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cpu_um 0 \
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cpu_idec 67 \
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cpu_pcload 31 \
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cpu_vfetch 0 \
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cpu_irupt 0 \
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ca_rd 133 \
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ca_wr 33 \
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ca_rdhit 133 \
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ca_wrhit 33 \
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ca_rdmem 0 \
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ca_wrmem 33
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rlc log " A4: dec+bne+inc @#ibus loop (test ibus access) -----"
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# use usr d page addr register (16 bit read/write) as easy ibus target
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set code {
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.include |lib/defs_mmu.mac|
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. = 1000
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stack:
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start: mov #32.,r0
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clr @#udpar
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1$: inc @#udpar
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dec r0
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bne 1$
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halt
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stop:
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cnt: .word 0
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}
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# cpu_idec: 99 = 96(inc+dec+bne) + 3(mov+clr+halt)
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# ca_rd: 101 = 4(mov+clr) + 128(inc+dec+bne) + 1(halt)
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tmpproc_dotest $cpu $code \
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cpu_km_prix 0 \
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cpu_km_pri0 -1 \
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cpu_km_wait 0 \
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cpu_sm 0 \
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cpu_um 0 \
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cpu_idec 99 \
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cpu_pcload 31 \
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cpu_vfetch 0 \
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cpu_irupt 0 \
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ca_rd 133 \
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ca_wr 0 \
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ca_rdhit 133 \
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ca_wrhit 0 \
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ca_rdmem 0 \
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ca_wrmem 0 \
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ib_rd 32 \
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ib_wr 33
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# -- Section B ---------------------------------------------------------------
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rlc log " B: test kern pri>0, super and user mode -------------------"
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rlc log " B1: kernel pri > 0 ---------------------------------"
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set code {
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.include |lib/defs_cpu.mac|
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. = 1000
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stack:
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start: mov #cp.pr7,@#cp.psw
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nop
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nop
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nop
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nop
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mov #cp.pr0,@#cp.psw
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halt
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stop:
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}
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tmpproc_dotest $cpu $code \
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cpu_km_prix -1 \
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cpu_km_pri0 -4 \
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cpu_km_wait 0 \
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cpu_sm 0 \
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cpu_um 0 \
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cpu_idec 7 \
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cpu_vfetch 0 \
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cpu_irupt 0 \
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cpu_pcload 0 \
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ca_rd 11 \
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ca_wr 0 \
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ca_rdhit 11 \
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ca_wrhit 0 \
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ca_rdmem 0 \
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ca_wrmem 0
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rlc log " B2: supervisor mode --------------------------------"
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set code {
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.include |lib/defs_cpu.mac|
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. = 1000
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stack:
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start: mov #cp.cms,@#cp.psw
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nop
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nop
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nop
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nop
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mov #cp.pr0,@#cp.psw
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halt
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stop:
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}
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tmpproc_dotest $cpu $code \
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cpu_km_prix 0 \
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cpu_km_pri0 -1 \
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cpu_km_wait 0 \
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cpu_sm -4 \
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cpu_um 0 \
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cpu_idec 7 \
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cpu_vfetch 0 \
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cpu_irupt 0 \
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cpu_pcload 0 \
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ca_rd 11 \
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ca_wr 0 \
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ca_rdhit 11 \
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ca_wrhit 0 \
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ca_rdmem 0 \
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ca_wrmem 0
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rlc log " B3: user mode --------------------------------------"
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set code {
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.include |lib/defs_cpu.mac|
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. = 1000
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stack:
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start: mov #cp.cmu,@#cp.psw
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nop
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nop
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nop
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nop
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mov #cp.pr0,@#cp.psw
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halt
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stop:
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}
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tmpproc_dotest $cpu $code \
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cpu_km_prix 0 \
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cpu_km_pri0 -1 \
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cpu_km_wait 0 \
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cpu_sm 0 \
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cpu_um -4 \
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cpu_idec 7 \
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cpu_vfetch 0 \
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cpu_irupt 0 \
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cpu_pcload 0 \
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ca_rd 11 \
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ca_wr 0 \
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ca_rdhit 11 \
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ca_wrhit 0 \
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ca_rdmem 0 \
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ca_wrmem 0
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# -- Section C ---------------------------------------------------------------
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rlc log " C: test vector fetch --------------------------------------"
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rlc log " C1: vector via trap instruction --------------------"
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set code {
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.include |lib/vec_cpucatch.mac|
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. = 1000
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stack:
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start: mov #vh.trp,@#v..trp
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mov #vh.emt,@#v..emt
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clr r0
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trap 1
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emt 1
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trap 2
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emt 2
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halt
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stop:
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vh.trp: rti
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vh.emt: inc r0
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rti
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}
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# cpu_idec: 14 = 8(main) +2*1(trap) + 2*2(emt)
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# ca_rd: 34 = 14+4(code) + 4*2(trap+emt) + 4*2(rti)
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# ca_wr: 34 = 2(code) + 4*2(trap+emt)
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# ca_pcload: 8 = 4(trap+emt) + 4(rti)
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tmpproc_dotest $cpu $code \
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cpu_km_prix 0 \
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cpu_km_pri0 -1 \
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cpu_km_wait 0 \
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cpu_sm 0 \
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cpu_um 0 \
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cpu_idec 14 \
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cpu_vfetch 4 \
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cpu_irupt 0 \
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cpu_pcload 8 \
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ca_rd 34 \
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ca_wr 10 \
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ca_rdhit 34 \
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ca_wrhit 10 \
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ca_rdmem 0 \
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ca_wrmem 10
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