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62 lines
1.8 KiB
VHDL
62 lines
1.8 KiB
VHDL
-- $Id: iob_reg_o.vhd 314 2010-07-09 17:38:41Z mueller $
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--
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-- Copyright 2007- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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-- This program is free software; you may redistribute and/or modify it under
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-- the terms of the GNU General Public License as published by the Free
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-- Software Foundation, either version 2, or at your option any later version.
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--
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-- This program is distributed in the hope that it will be useful, but
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-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
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-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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-- for complete details.
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--
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------------------------------------------------------------------------------
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-- Module Name: iob_reg_i - syn
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-- Description: Registered IOB, output only
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--
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-- Dependencies: -
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-- Test bench: -
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-- Target Devices: generic Spartan, Virtex
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-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25
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-- Revision History:
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-- Date Rev Version Comment
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-- 2007-12-16 101 1.0.1 add INIT generic port
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-- 2007-12-08 100 1.0 Initial version
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use work.slvtypes.all;
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use work.xlib.all;
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entity iob_reg_o is -- registered IOB, output
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generic (
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INIT : slbit := '0'); -- initial state
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port (
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CLK : in slbit; -- clock
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CE : in slbit := '1'; -- clock enable
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DO : in slbit; -- output data
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PAD : out slbit -- i/o pad
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);
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end iob_reg_o;
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architecture syn of iob_reg_o is
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begin
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IOB : iob_reg_o_gen
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generic map (
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DWIDTH => 1,
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INIT => INIT)
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port map (
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CLK => CLK,
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CE => CE,
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DO(0) => DO,
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PAD(0) => PAD
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);
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end syn;
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