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674762d6d8
- s7_cmt_1ce1ce: add clock generator block used in many 7-Series designs - sys_gen/*/*: use s7_cmt_1ce1ce in 7-Series designs - tbcore_rlink: wait 40 cycles after CONF_DONE - serport_master_tb: add 100 ps RXSD,TXSD delay to allow clock jitter
327 lines
16 KiB
VHDL
327 lines
16 KiB
VHDL
-- $Id: bpgenlib.vhd 1086 2018-12-16 18:29:55Z mueller $
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--
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-- Copyright 2011-2018 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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-- This program is free software; you may redistribute and/or modify it under
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-- the terms of the GNU General Public License as published by the Free
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-- Software Foundation, either version 3, or (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful, but
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-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
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-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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-- for complete details.
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--
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------------------------------------------------------------------------------
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-- Package Name: bpgenlib
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-- Description: Generic Board/Part components
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--
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-- Dependencies: -
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-- Tool versions: ise 12.1-14.7; viv 2014.4-2018.2; ghdl 0.26-0.34
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-- Revision History:
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-- Date Rev Version Comment
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-- 2018-12-16 1086 1.2.3 add s7_cmt_1ce1ce
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-- 2018-08-11 1038 1.2.2 add rgbdrv_3x2mux
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-- 2017-06-05 907 1.2.1 rgbdrv_analog: add ACTLOW generic
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-- 2016-02-27 737 1.2 add rgbdrv entity
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-- 2015-01-24 637 1.1.2 add generics to sn_humanio and sn_7segctl
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-- 2013-09-21 534 1.1.1 add bp_rs232_4l4l_iob
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-- 2013-01-26 476 1.1 moved rbus depended components to bpgenrbuslib
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-- 2013-01-06 472 1.0.7 add sn_humanio_demu_rbus
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-- 2011-11-16 426 1.0.6 now numeric_std clean
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-- 2011-10-10 413 1.0.5 add sn_humanio_demu
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-- 2011-08-07 404 1.0.4 add RELAY generic for bp_rs232_2l4l_iob
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-- 2011-08-06 403 1.0.3 add RESET port for bp_rs232_2l4l_iob
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-- 2011-07-09 391 1.0.2 move in bp_rs232_2l4l_iob from s3boardlib
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-- 2011-07-08 390 1.0.1 move in sn_(4x7segctl|humanio*) from s3boardlib
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-- 2011-07-01 386 1.0 Initial version (with rs232_iob's and bp_swibtnled)
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.slvtypes.all;
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package bpgenlib is
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component bp_rs232_2line_iob is -- iob's for 2 line rs232 (RXD,TXD)
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port (
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CLK : in slbit; -- clock
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RXD : out slbit; -- receive data (board view)
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TXD : in slbit; -- transmit data (board view)
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I_RXD : in slbit; -- pad-i: receive data (board view)
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O_TXD : out slbit -- pad-o: transmit data (board view)
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);
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end component;
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component bp_rs232_4line_iob is -- iob's for 4 line rs232 (w/ RTS,CTS)
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port (
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CLK : in slbit; -- clock
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RXD : out slbit; -- receive data (board view)
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TXD : in slbit; -- transmit data (board view)
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CTS_N : out slbit; -- clear to send (act. low)
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RTS_N : in slbit; -- request to send (act. low)
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I_RXD : in slbit; -- pad-i: receive data (board view)
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O_TXD : out slbit; -- pad-o: transmit data (board view)
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I_CTS_N : in slbit; -- pad-i: clear to send (act. low)
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O_RTS_N : out slbit -- pad-o: request to send (act. low)
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);
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end component;
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component bp_rs232_2l4l_iob is -- iob's for dual 2l+4l rs232, w/ select
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generic (
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RELAY : boolean := false); -- add a relay stage towards IOB's
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port (
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CLK : in slbit; -- clock
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RESET : in slbit := '0'; -- reset
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SEL : in slbit; -- select, '0' for port 0
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RXD : out slbit; -- receive data (board view)
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TXD : in slbit; -- transmit data (board view)
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CTS_N : out slbit; -- clear to send (act. low)
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RTS_N : in slbit; -- request to send (act. low)
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I_RXD0 : in slbit; -- pad-i: p0: receive data (board view)
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O_TXD0 : out slbit; -- pad-o: p0: transmit data (board view)
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I_RXD1 : in slbit; -- pad-i: p1: receive data (board view)
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O_TXD1 : out slbit; -- pad-o: p1: transmit data (board view)
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I_CTS1_N : in slbit; -- pad-i: p1: clear to send (act. low)
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O_RTS1_N : out slbit -- pad-o: p1: request to send (act. low)
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);
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end component;
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component bp_rs232_4l4l_iob is -- iob's for dual 4l+4l rs232, w/ select
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generic (
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RELAY : boolean := false); -- add a relay stage towards IOB's
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port (
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CLK : in slbit; -- clock
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RESET : in slbit := '0'; -- reset
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SEL : in slbit; -- select, '0' for port 0
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RXD : out slbit; -- receive data (board view)
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TXD : in slbit; -- transmit data (board view)
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CTS_N : out slbit; -- clear to send (act. low)
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RTS_N : in slbit; -- request to send (act. low)
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I_RXD0 : in slbit; -- pad-i: p0: receive data (board view)
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O_TXD0 : out slbit; -- pad-o: p0: transmit data (board view)
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I_CTS0_N : in slbit; -- pad-i: p0: clear to send (act. low)
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O_RTS0_N : out slbit; -- pad-o: p0: request to send (act. low)
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I_RXD1 : in slbit; -- pad-i: p1: receive data (board view)
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O_TXD1 : out slbit; -- pad-o: p1: transmit data (board view)
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I_CTS1_N : in slbit; -- pad-i: p1: clear to send (act. low)
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O_RTS1_N : out slbit -- pad-o: p1: request to send (act. low)
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);
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end component;
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component bp_swibtnled is -- generic SWI, BTN and LED handling
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generic (
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SWIDTH : positive := 4; -- SWI port width
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BWIDTH : positive := 4; -- BTN port width
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LWIDTH : positive := 4; -- LED port width
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DEBOUNCE : boolean := true); -- instantiate debouncer for SWI,BTN
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port (
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CLK : in slbit; -- clock
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RESET : in slbit := '0'; -- reset
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CE_MSEC : in slbit; -- 1 ms clock enable
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SWI : out slv(SWIDTH-1 downto 0); -- switch settings, debounced
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BTN : out slv(BWIDTH-1 downto 0); -- button settings, debounced
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LED : in slv(LWIDTH-1 downto 0); -- led data
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I_SWI : in slv(SWIDTH-1 downto 0); -- pad-i: switches
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I_BTN : in slv(BWIDTH-1 downto 0); -- pad-i: buttons
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O_LED : out slv(LWIDTH-1 downto 0) -- pad-o: leds
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);
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end component;
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component sn_7segctl is -- 7 segment display controller
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generic (
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DCWIDTH : positive := 2; -- digit counter width (2 or 3)
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CDWIDTH : positive := 6); -- clk divider width (must be >= 5)
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port (
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CLK : in slbit; -- clock
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DIN : in slv(4*(2**DCWIDTH)-1 downto 0); -- data 16 or 32
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DP : in slv((2**DCWIDTH)-1 downto 0); -- decimal points 4 or 8
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ANO_N : out slv((2**DCWIDTH)-1 downto 0); -- anodes (act.low) 4 or 8
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SEG_N : out slv8 -- segements (act.low)
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);
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end component;
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component sn_humanio is -- human i/o handling: swi,btn,led,dsp
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generic (
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SWIDTH : positive := 8; -- SWI port width
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BWIDTH : positive := 4; -- BTN port width
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LWIDTH : positive := 8; -- LED port width
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DCWIDTH : positive := 2; -- digit counter width (2 or 3)
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DEBOUNCE : boolean := true); -- instantiate debouncer for SWI,BTN
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port (
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CLK : in slbit; -- clock
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RESET : in slbit := '0'; -- reset
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CE_MSEC : in slbit; -- 1 ms clock enable
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SWI : out slv(SWIDTH-1 downto 0); -- switch settings, debounced
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BTN : out slv(BWIDTH-1 downto 0); -- button settings, debounced
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LED : in slv(LWIDTH-1 downto 0); -- led data
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DSP_DAT : in slv(4*(2**DCWIDTH)-1 downto 0); -- display data
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DSP_DP : in slv((2**DCWIDTH)-1 downto 0); -- display decimal points
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I_SWI : in slv(SWIDTH-1 downto 0); -- pad-i: switches
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I_BTN : in slv(BWIDTH-1 downto 0); -- pad-i: buttons
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O_LED : out slv(LWIDTH-1 downto 0); -- pad-o: leds
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O_ANO_N : out slv((2**DCWIDTH)-1 downto 0); -- pad-o: disp: anodes (act.low)
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O_SEG_N : out slv8 -- pad-o: disp: segments (act.low)
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);
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end component;
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component sn_humanio_demu is -- human i/o handling: swi,btn,led only
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generic (
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DEBOUNCE : boolean := true); -- instantiate debouncer for SWI,BTN
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port (
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CLK : in slbit; -- clock
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RESET : in slbit := '0'; -- reset
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CE_MSEC : in slbit; -- 1 ms clock enable
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SWI : out slv8; -- switch settings, debounced
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BTN : out slv4; -- button settings, debounced
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LED : in slv8; -- led data
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DSP_DAT : in slv16; -- display data
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DSP_DP : in slv4; -- display decimal points
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I_SWI : in slv8; -- pad-i: switches
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I_BTN : in slv6; -- pad-i: buttons
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O_LED : out slv8 -- pad-o: leds
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);
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end component;
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component rgbdrv_master is -- rgbled driver: master
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generic (
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DWIDTH : positive := 8); -- dimmer width
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port (
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CLK : in slbit; -- clock
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RESET : in slbit := '0'; -- reset
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CE_USEC : in slbit; -- 1 us clock enable
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RGBCNTL : out slv3; -- rgb control
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DIMCNTL : out slv(DWIDTH-1 downto 0) -- dim control
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);
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end component;
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component rgbdrv_analog is -- rgbled driver: analog channel
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generic (
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DWIDTH : positive := 8; -- dimmer width
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ACTLOW : slbit := '0'); -- invert output polarity
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port (
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CLK : in slbit; -- clock
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RESET : in slbit := '0'; -- reset
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RGBCNTL : in slv3; -- rgb control
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DIMCNTL : in slv(DWIDTH-1 downto 0);-- dim control
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DIMR : in slv(DWIDTH-1 downto 0); -- dim red
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DIMG : in slv(DWIDTH-1 downto 0); -- dim green
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DIMB : in slv(DWIDTH-1 downto 0); -- dim blue
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O_RGBLED : out slv3 -- pad-o: rgb led
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);
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end component;
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component rgbdrv_binary is -- rgbled driver: binary channel
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generic (
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DWIDTH : positive := 8); -- dimmer width
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port (
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CLK : in slbit; -- clock
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RESET : in slbit := '0'; -- reset
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RGBCNTL : in slv3; -- rgb control
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DIMCNTL : in slv(DWIDTH-1 downto 0);-- dim control
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DIM : in slv(DWIDTH-1 downto 0); -- dim
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ENARGB : in slv3; -- enable [0] red [1] green [2] blue
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O_RGBLED : out slv3 -- pad-o: rgb led
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);
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end component;
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component rgbdrv_3x4mux is -- rgbled driver: mux three 4bit inputs
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port (
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CLK : in slbit; -- clock
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RESET : in slbit := '0'; -- reset
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CE_USEC : in slbit; -- 1 us clock enable
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DATR : in slv4; -- red data
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DATG : in slv4; -- green data
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DATB : in slv4; -- blue data
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O_RGBLED0 : out slv3; -- pad-o: rgb led 0
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O_RGBLED1 : out slv3; -- pad-o: rgb led 1
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O_RGBLED2 : out slv3; -- pad-o: rgb led 2
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O_RGBLED3 : out slv3 -- pad-o: rgb led 3
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);
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end component;
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component rgbdrv_3x2mux is -- rgbled driver: mux three 2bit inputs
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port (
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CLK : in slbit; -- clock
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RESET : in slbit := '0'; -- reset
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CE_USEC : in slbit; -- 1 us clock enable
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DATR : in slv2; -- red data
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DATG : in slv2; -- green data
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DATB : in slv2; -- blue data
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O_RGBLED0 : out slv3; -- pad-o: rgb led 0
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O_RGBLED1 : out slv3 -- pad-o: rgb led 1
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);
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end component;
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component s7_cmt_1ce1ce is -- clocking block: 2 clk+CEs
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generic (
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CLKIN_PERIOD : real := 10.0; -- CLKIN period (def is 10.0 ns)
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CLKIN_JITTER : real := 0.01; -- CLKIN jitter (def is 10 ps)
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STARTUP_WAIT : boolean := false; -- hold FPGA startup till LOCKED
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CLK0_VCODIV : positive := 1; -- clk0: vco clock divide
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CLK0_VCOMUL : positive := 1; -- clk0: vco clock multiply
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CLK0_OUTDIV : positive := 1; -- clk0: output divide
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CLK0_GENTYPE : string := "PLL"; -- clk0: PLL or MMCM
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CLK0_CDUWIDTH : positive := 7; -- clk0: usec clock divider width
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CLK0_USECDIV : positive := 50; -- clk0: divider ratio for usec pulse
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CLK0_MSECDIV : positive := 1000; -- clk0: divider ratio for msec pulse
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CLK1_VCODIV : positive := 1; -- clk1: vco clock divide
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CLK1_VCOMUL : positive := 1; -- clk1: vco clock multiply
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CLK1_OUTDIV : positive := 1; -- clk1: output divide
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CLK1_GENTYPE : string := "MMCM"; -- clk1: PLL or MMCM
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CLK1_CDUWIDTH : positive := 7; -- clk1: usec clock divider width
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CLK1_USECDIV : positive := 50; -- clk1: divider ratio for usec pulse
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CLK1_MSECDIV : positive := 1000); -- clk1: divider ratio for msec pulse
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port (
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CLKIN : in slbit; -- clock input
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CLK0 : out slbit; -- clk0: clock output
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CE0_USEC : out slbit; -- clk0: usec pulse
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CE0_MSEC : out slbit; -- clk0: msec pulse
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CLK1 : out slbit; -- clk1: clock output
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CE1_USEC : out slbit; -- clk1: usec pulse
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CE1_MSEC : out slbit; -- clk1: msec pulse
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LOCKED : out slbit -- all PLL/MMCM locked
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);
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end component;
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component s7_cmt_1ce1ce2c is -- clocking block: 2 clk+CEs; 2 clk
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generic (
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CLKIN_PERIOD : real := 10.0; -- CLKIN period (def is 10.0 ns)
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CLKIN_JITTER : real := 0.01; -- CLKIN jitter (def is 10 ps)
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STARTUP_WAIT : boolean := false; -- hold FPGA startup till LOCKED
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CLK0_VCODIV : positive := 1; -- clk0: vco clock divide
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CLK0_VCOMUL : positive := 1; -- clk0: vco clock multiply
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CLK0_OUTDIV : positive := 1; -- clk0: output divide
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CLK0_GENTYPE : string := "PLL"; -- clk0: PLL or MMCM
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CLK0_CDUWIDTH : positive := 7; -- clk0: usec clock divider width
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CLK0_USECDIV : positive := 50; -- clk0: divider ratio for usec pulse
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CLK0_MSECDIV : positive := 1000; -- clk0: divider ratio for msec pulse
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CLK1_VCODIV : positive := 1; -- clk1: vco clock divide
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CLK1_VCOMUL : positive := 1; -- clk1: vco clock multiply
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CLK1_OUTDIV : positive := 1; -- clk1: output divide
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CLK1_GENTYPE : string := "MMCM"; -- clk1: PLL or MMCM
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CLK1_CDUWIDTH : positive := 7; -- clk1: usec clock divider width
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CLK1_USECDIV : positive := 50; -- clk1: divider ratio for usec pulse
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CLK1_MSECDIV : positive := 1000; -- clk1: divider ratio for msec pulse
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CLK23_VCODIV : positive := 1; -- clk2+3: vco clock divide
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CLK23_VCOMUL : positive := 1; -- clk2+3: vco clock multiply
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CLK2_OUTDIV : positive := 1; -- clk2: output divide
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CLK3_OUTDIV : positive := 1; -- clk3: output divide
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CLK23_GENTYPE : string := "PLL"); -- clk2+3: PLL or MMCM
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port (
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CLKIN : in slbit; -- clock input
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CLK0 : out slbit; -- clk0: clock output
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CE0_USEC : out slbit; -- clk0: usec pulse
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CE0_MSEC : out slbit; -- clk0: msec pulse
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CLK1 : out slbit; -- clk1: clock output
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CE1_USEC : out slbit; -- clk1: usec pulse
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CE1_MSEC : out slbit; -- clk1: msec pulse
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CLK2 : out slbit; -- clk2: clock output
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CLK3 : out slbit; -- clk3: clock output
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LOCKED : out slbit -- all PLL/MMCM locked
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);
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end component;
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end package bpgenlib;
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