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46 lines
1.2 KiB
Makefile
46 lines
1.2 KiB
Makefile
# $Id: Makefile 1069 2018-11-16 17:11:30Z mueller $
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#
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# Revision History:
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# Date Rev Version Comment
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# 2018-11-16 1069 1.0 Initial version
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#
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EXE_all = tb_sramif2migui_core_ba3_bram
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EXE_all += tb_sramif2migui_core_ba3_msim
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EXE_all += tb_sramif2migui_core_ba4_bram
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EXE_all += tb_sramif2migui_core_ba4_msim
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#
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# reference board for test synthesis is Artix-7 based Nexys4
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ifndef XTW_BOARD
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XTW_BOARD=nexys4
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endif
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include ${RETROBASE}/rtl/make_viv/viv_default_$(XTW_BOARD).mk
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#
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.PHONY : all all_ssim all_osim clean
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.PHONY : all_XSim all_XSim_ssim all_XSim_osim all_XSim_tsim
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#
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all : $(EXE_all)
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all_ssim : $(EXE_all:=_ssim)
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all_osim : $(EXE_all:=_osim)
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#
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all_XSim : $(EXE_all:=_XSim)
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all_XSim_ssim : $(EXE_all:=_XSim_ssim)
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all_XSim_osim : $(EXE_all:=_XSim_osim)
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all_XSim_tsim : $(EXE_all:=_XSim_tsim)
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#
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clean : viv_clean ghdl_clean xsim_clean
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#
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#-----
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#
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include ${RETROBASE}/rtl/make_viv/generic_ghdl.mk
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include ${RETROBASE}/rtl/make_viv/generic_xsim.mk
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include ${RETROBASE}/rtl/make_viv/generic_vivado.mk
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#
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VBOM_all = $(wildcard *.vbom)
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#
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ifndef DONTINCDEP
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include $(VBOM_all:.vbom=.dep_vsyn)
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include $(VBOM_all:.vbom=.dep_ghdl)
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include $(VBOM_all:.vbom=.dep_vsim)
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endif
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#
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