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148 lines
4.6 KiB
VHDL
148 lines
4.6 KiB
VHDL
-- $Id: rlink_mon.vhd 348 2010-12-26 15:23:44Z mueller $
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--
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-- Copyright 2007-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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-- This program is free software; you may redistribute and/or modify it under
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-- the terms of the GNU General Public License as published by the Free
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-- Software Foundation, either version 2, or at your option any later version.
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--
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-- This program is distributed in the hope that it will be useful, but
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-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
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-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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-- for complete details.
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--
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------------------------------------------------------------------------------
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-- Module Name: rlink_mon - sim
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-- Description: rlink monitor (for tb's)
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--
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-- Dependencies: -
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-- Test bench: -
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-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 12.1; ghdl 0.18-0.29
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--
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-- Revision History:
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-- Date Rev Version Comment
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-- 2010-12-24 347 3.0.1 rename: CP_*->RL->*
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-- 2010-12-22 346 3.0 renamed rritb_cpmon -> rlink_mon
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-- 2010-06-11 303 2.5.1 fix data9 assignment, always proper width now
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-- 2010-06-07 302 2.5 use sop/eop framing instead of soc+chaining
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-- 2008-03-24 129 1.0.1 CLK_CYCLE now 31 bits
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-- 2007-09-09 81 1.0 Initial version
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_textio.all;
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use std.textio.all;
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use work.slvtypes.all;
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use work.simlib.all;
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use work.rlinklib.all;
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entity rlink_mon is -- rlink monitor
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generic (
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DWIDTH : positive := 9); -- data port width (8 or 9)
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port (
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CLK : in slbit; -- clock
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CLK_CYCLE : in slv31 := (others=>'0'); -- clock cycle number
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ENA : in slbit := '1'; -- enable monitor output
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RL_DI : in slv(DWIDTH-1 downto 0); -- rlink: data in
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RL_ENA : in slbit; -- rlink: data enable
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RL_BUSY : in slbit; -- rlink: data busy
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RL_DO : in slv(DWIDTH-1 downto 0); -- rlink: data out
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RL_VAL : in slbit; -- rlink: data valid
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RL_HOLD : in slbit -- rlink: data hold
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);
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end rlink_mon;
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architecture sim of rlink_mon is
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begin
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assert DWIDTH=8 or DWIDTH=9
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report "assert(DWIDTH=8 or DWIDTH=9)" severity failure;
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proc_moni: process
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variable oline : line;
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variable nbusy : integer := 0;
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variable nhold : integer := 0;
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procedure write_val(L: inout line;
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data: in slv(DWIDTH-1 downto 0);
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nwait: in integer;
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txt1: in string;
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txt2: in string) is
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variable data9 : slv9 := (others=>'0');
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begin
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writetimestamp(L, CLK_CYCLE, txt1);
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if DWIDTH = 9 then
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write(L, data(data'left), right, 1);
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else
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write(L, string'(" "));
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end if;
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write(L, data(7 downto 0), right, 9);
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if nwait > 0 then
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write(L, txt2);
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write(L, nwait);
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end if;
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if DWIDTH=9 and data(data'left)='1' then
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-- a copy to data9 needed to allow following case construct
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-- using data directly gives a 'subtype is not locally static' error
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data9 := (others=>'0');
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data9(data'range) := data;
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write(L, string'(" comma"));
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case data9 is
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when c_rlink_dat_idle => write(L, string'(" idle"));
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when c_rlink_dat_sop => write(L, string'(" sop"));
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when c_rlink_dat_eop => write(L, string'(" eop"));
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when c_rlink_dat_nak => write(L, string'(" nak"));
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when c_rlink_dat_attn => write(L, string'(" attn"));
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when others => null;
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end case;
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end if;
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writeline(output, L);
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end procedure write_val;
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begin
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loop
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if ENA='0' then -- if disabled
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wait until ENA='1'; -- stall process till enabled
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end if;
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wait until CLK'event and CLK='1'; -- check at end of clock cycle
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if RL_ENA = '1' then
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if RL_BUSY = '1' then
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nbusy := nbusy + 1;
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else
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write_val(oline, RL_DI, nbusy, ": rlrx ", " nbusy=");
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nbusy := 0;
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end if;
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else
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nbusy := 0;
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end if;
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if RL_VAL = '1' then
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if RL_HOLD = '1' then
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nhold := nhold + 1;
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else
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write_val(oline, RL_DO, nhold, ": rltx ", " nhold=");
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nhold := 0;
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end if;
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else
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nhold := 0;
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end if;
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end loop;
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end process proc_moni;
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end sim;
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