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16ce5b2091
- migrate to ibus protocol verion 2 - nexys2 systems now with DCM derived system clock supported - sys_w11a_n2 now runs with 58 MHz clksys
56 lines
1.6 KiB
VHDL
56 lines
1.6 KiB
VHDL
-- $Id: simclkcnt.vhd 338 2010-11-13 22:19:25Z mueller $
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--
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-- Copyright 2010- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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-- This program is free software; you may redistribute and/or modify it under
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-- the terms of the GNU General Public License as published by the Free
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-- Software Foundation, either version 2, or at your option any later version.
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--
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-- This program is distributed in the hope that it will be useful, but
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-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
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-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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-- for complete details.
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--
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------------------------------------------------------------------------------
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-- Module Name: simclkcnt - sim
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-- Description: test bench system clock cycle counter
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--
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-- Dependencies: -
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-- Test bench: -
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-- Target Devices: generic
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-- Tool versions: xst 12.1; ghdl 0.29
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--
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-- Revision History:
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-- Date Rev Version Comment
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-- 2010-11-13 72 1.0 Initial version
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use work.slvtypes.all;
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entity simclkcnt is -- test bench system clock cycle counter
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port (
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CLK : in slbit; -- clock
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CLK_CYCLE : out slv31 -- clock cycle number
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);
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end entity simclkcnt;
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architecture sim of simclkcnt is
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signal R_CLKCNT : slv31 := (others=>'0');
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begin
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proc_clk: process (CLK)
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begin
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if CLK'event and CLK='1' then
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R_CLKCNT <= unsigned(R_CLKCNT) + 1;
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end if;
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end process proc_clk;
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CLK_CYCLE <= R_CLKCNT;
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end sim;
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