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41 lines
1.4 KiB
VHDL
41 lines
1.4 KiB
VHDL
-- $Id: pdp11_sim.vhd 314 2010-07-09 17:38:41Z mueller $
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--
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-- Copyright 2006-2007 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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-- This program is free software; you may redistribute and/or modify it under
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-- the terms of the GNU General Public License as published by the Free
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-- Software Foundation, either version 2, or at your option any later version.
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--
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-- This program is distributed in the hope that it will be useful, but
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-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
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-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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-- for complete details.
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--
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------------------------------------------------------------------------------
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-- Package Name: pdp11_sim
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-- Description: Definitions for simulations
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--
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-- Dependencies: -
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-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25
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-- Revision History:
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-- Date Rev Version Comment
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-- 2007-10-12 88 1.0.2 avoid ieee.std_logic_unsigned, use cast to unsigned
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-- 2007-06-14 56 1.0.1 Use slvtypes.all
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-- 2007-05-12 26 1.0 Initial version
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_textio.all;
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use std.textio.all;
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package pdp11_sim is
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constant clock_period : time := 20 ns;
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constant clock_offset : time := 200 ns;
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constant setup_time : time := 5 ns;
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constant c2out_time : time := 5 ns;
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end package pdp11_sim;
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