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0c395856d7
- add fifo_simple_dram: simple fifo with CE/WE interface, dram based - add test benches for fifo_simple_dram, fifo_2c_dram, and fifo_2c_dram2 - add simclkv: test bench clock generator with variable period
22 lines
535 B
YAML
22 lines
535 B
YAML
# $Id: tbrun.yml 1109 2019-02-09 13:36:41Z mueller $
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#
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# Revision History:
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# Date Rev Version Comment
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# 2019-02-01 1109 1.1 Add tb_fifo_simple_dram
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# 2016-08-12 797 1.0 Initial version
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#
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- default:
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mode: ${viv_modes}
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#
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- tag: [default, viv, memlib, fifo_simple_dram]
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test: |
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tbrun_tbw tb_fifo_simple_dram${ms}
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- tag: [default, viv, memlib, fifo_2c_dram]
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test: |
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tbrun_tbw tb_fifo_2c_dram${ms}
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- tag: [default, viv, memlib, fifo_2c_dram2]
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test: |
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tbrun_tbw tb_fifo_2c_dram2${ms}
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