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faf596e531
- add -emcancel; drop em 'cancel' when -t-ib - print ru after em,ib, best for reg from mem cases - map r6,r7 to sp,pc for rdst,1reg,rsrc instructions
252 lines
7.2 KiB
Groff
252 lines
7.2 KiB
Groff
.\" -*- nroff -*-
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.\" $Id: tmuconv.1 1261 2022-07-23 16:15:03Z mueller $
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.\" SPDX-License-Identifier: GPL-3.0-or-later
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.\" Copyright 2013-2022 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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.\"
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.\" ------------------------------------------------------------------
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.
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.TH TMUCONV 1 2022-07-18 "Retro Project" "Retro Project Manual"
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.\" ------------------------------------------------------------------
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.SH NAME
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tmuconv \- convert w11a tmu output into human readable format
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.\" ------------------------------------------------------------------
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.SH SYNOPSIS
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.
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.SY tmuconv
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.RI [ OPTION ]...
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.I FILE
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.
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.SY tmuconv
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.B \-\-help
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.YS
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.
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.\" ------------------------------------------------------------------
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.SH DESCRIPTION
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Converts the output of the \fBw11a\fR trace and monitoring unit (tmu)
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into a human readable format. If no options are given, the default
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output is \fB\-t_id\fR \fB\-t_vf\fR.
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.
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.\" ------------------------------------------------------------------
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.SH OPTIONS
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.
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.\" ----------------------------------------------
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.IP "\fB\-dump\fR"
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dump all information.
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.
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.\" ----------------------------------------------
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.IP "\fB\-cdump\fR"
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dump only changes relative to previous cycle.
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.
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.\" ----------------------------------------------
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.IP "\fB\-emcancel\fR"
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show em 'cancel' cycles when \fB\-t_ib\fR active.
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.
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.\" ----------------------------------------------
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.IP "\fB\-t_id\fR"
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trace instruction decodes.
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.
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.\" ----------------------------------------------
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.IP "\fB\-t_ru\fR"
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trace register updates.
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.
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.\" ----------------------------------------------
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.IP "\fB\-t_em\fR"
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trace em transactions (external memory bus).
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em transactions that converted to an ib transaction are labeled 'cancel'.
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They are not shown when \fB\-t_ib\fR is active and no \fB\-emcancel\fR option
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is given. This gives the most readable output for \fB\-t_all\fR.
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Reads from well known vector addresses are labeled 'VFETCH'.
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This is very helpful for the detection of interrupts.
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See also \fB\-t_vf\fR.
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Note: every read from location 200 will therefore be labeled 'VFETCH 200 LP11',
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also when it is an instruction fetch for a 'JMP' instruction in old maindecs
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with start address 200.
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.
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.\" ----------------------------------------------
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.IP "\fB\-t_vf\fR"
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trace only vector fetch em transactions (subset of \fB\-t_em\fR)
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.
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.\" ----------------------------------------------
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.IP "\fB\-t_ib\fR"
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trace ib transactions (ibus cycles). em 'cancel' transactions are not shown
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unless the \fB\-emcancel\fR option is given.
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.
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.\" ----------------------------------------------
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.IP "\fB\-t_all\fR"
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trace all, equivalent to \fB\-t_id\fR \fB\-t_ru\fR \fB\-t_em\fR \fB\-t_ib\fR
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.
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.\" ----------------------------------------------
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.IP "\fB\-help\fR"
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print full help text and exit.
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.
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.\" ------------------------------------------------------------------
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.SH TRACE OUTPUT FORMAT
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Each output line starts with the cycle number and the trace type.
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The format of the rest of the line depends on trace type.
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\fB\-t_id\fP: the instruction decode trace gives
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.RS 2
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.PD 0
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.IP "-" 2
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the PC of the instruction
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.IP "-"
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the PSW at the beginning(!) of the instruction
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.IP "-"
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the instruction word (as loaded into the instruction register)
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.IP "-"
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the instruction in MACRO-11 syntax
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.IP "-"
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the number of cycles of the previous(!) instruction
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.PD
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.RE
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.PP
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.EX
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cycle pc psw ireg code nc
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71587 id 006054 000011 012410 mov (r4)+,(r0) (4)
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71683 id 002146 000340 116767 movb nnn(pc),nnn(pc) (9)
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.EE
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\fB\-t_ru\fP: the register update trace gives
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.RS 2
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.PD 0
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.IP "-" 2
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the byte update indicator
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.IP "-"
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the register set (0 pr 1)
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.IP "-"
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the register number (0 to 7)
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.IP "-"
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the loaded data value
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.IP "-"
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in case of a stack pointer update the values of kernel, supervisor and user
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stack pointers
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.IP "-"
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in case of an R0-R5 update the values of all these six registers
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.IP "-"
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the symbolic name of the register
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.PD
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.RE
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.PP
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.EX
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cycle b sr data
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71578 ru 0 07 006102 pc
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71649 ru 0 06 002000 002000*------ ------ ksp
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71634 ru 0 04 010752 006110 006112 177776 010752 010752*010642 r04
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.EE
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\fB\-t_em\fP: the memory transaction trace gives
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.RS 2
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.PD 0
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.IP "-" 2
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the r/w flag
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.IP "-"
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the byte enables
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.IP "-"
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the memory address (as 22bit number)
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.IP "-"
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the data written to memory
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.IP "-"
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the data received from memory
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.IP "-"
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four flag bits 'crwh' indicating cancel, read, write, and cache-hit
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.IP "-"
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the number of extra wait cycles
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.IP "-"
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in case of vector fetches and associated stack pushes some descriptive text
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.PD
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.RE
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.PP
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.EX
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cycle be addr wdat rdat crwh nc
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11374 em w 11 00000004 000006 0010 (1)
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52574 em r 11 00002164 177624 0101 (1)
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52530 em r 11 00000020 002142 0101 (1)
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52532 em r 11 00000022 000340 0101 (1) VFETCH 020 IOT
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52536 em w 11 00001776 000017 0010 (1)
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52538 em w 11 00001774 004316 0010 (1) SPUSH
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.EE
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\fB\-t_ib\fP: the ibus transaction trace gives
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.RS 2
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.PD 0
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.IP "-" 2
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two flag bits 'cr' indicating console and remote access
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.IP "-"
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two flag bits 'rm' indicating read/write and modify
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.IP "-"
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the byte enables
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.IP "-"
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the bus address (as 16bit number)
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.IP "-"
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the data written to bus
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.IP "-"
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the data received from bus
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.IP "-"
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the acknowledge flag
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.IP "-"
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the number of extra wait cycles
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.IP "-"
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if known, the symbolic name of the register
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.PD
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.RE
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.PP
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.EX
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cycle cr rmbe addr wdat rdat a nc name
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988 ib cr r 11 177500 000000 1 (0) ii.acr
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52583 ib -- w 11 177570 000001 1 (0) sdreg
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70729 ib -- r 11 177776 000004 1 (0) psw
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.EE
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The w11 CPU starts a cache cycle for each read or write, and cancels the
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cache request when an ibus access is detected. These transactions are usually
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suppressed when \fB\-t_ib\fP is active but are shown when \fB\-emcancel\fP
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is given, resulting in output like
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.EX
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52582 em w 11 00177570 000001 cancel 1000 (1)
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52583 ib -- w 11 177570 000001 1 (0) sdreg
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.EE
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.
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.\" ------------------------------------------------------------------
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.SH EXAMPLES
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.IP "\fBtmuconv --t_id --t_em --t_ib tmu_ofile\fR" 4
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Produces an output with all instruction decodes and external memory interface
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and ibus transactions. The execution of a 'bisb #4,4(r4)' instruction which
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accesses the output CSR of a DL11 interface will look like
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.EX
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429 id 002002 000340 152764 bisb #nnn,nnn(r4) (5)
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431 em r 01 00002004 000004 0100 (1)
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433 em r 11 00002006 000004 0100 (1)
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436 ib -- rm01 177564 000200 1 (0) to.csr
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439 ib -- wm01 177564 000204 1 (0) to.csr
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.EE
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and shows the ibus read-modify-write.
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.IP "\fBtmuconv --t_all tmu_ofile\fR" 4
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Like above, in addition, also all register updates are shown. The execution
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of a 'cmp (r2),(r4)+' where r2 points to the psw will look like
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.EX
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934 id 003014 000011 021224 cmp (r2),(r4)+ (9)
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937 ib -- r 11 177776 000011 1 (0) psw
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939 ru 0 04 005676 003036 003040 177776 005700 005676*005570 r04
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940 em r 11 00005674 000011 0101 (1)
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.EE
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.\" ------------------------------------------------------------------
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.SH "SEE ALSO"
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.BR ti_rri (1)
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.\" ------------------------------------------------------------------
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.SH AUTHOR
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Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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