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59 lines
2.0 KiB
Tcl
59 lines
2.0 KiB
Tcl
# $Id: viv_tools_model.tcl 1194 2019-07-20 07:43:21Z mueller $
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# SPDX-License-Identifier: GPL-3.0-or-later
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# Copyright 2015-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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#
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# Revision History:
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# Date Rev Version Comment
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# 2016-06-24 778 1.1 support mode [sor]sim_vhdl [sorepd]sim_veri
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# 2016-06-19 777 1.0.1 use full absolute path name for sdf annotate
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# 2015-02-14 646 1.0 Initial version
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#
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# --------------------------------------------------------------------
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# supported modes
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# base ----- func ----- timing
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# vhdl veri veri
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# post synth _syn.dcp ssim_vhd ssim_v esim_v
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# post phys_opt _opt.dcp osim_vhd osim_v psim_v
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# post route _rou.dcp rsim_vhd rsim_v tsim_v
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#
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proc rvtb_default_model {stem mode} {
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if {[regexp -- {^([sor])sim_(vhd|v)$} $mode matched type lang] ||
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[regexp -- {^([ept])sim_(v)$} $mode matched type lang]} {
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switch $type {
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s -
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e {open_checkpoint "${stem}_syn.dcp"}
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o -
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p {open_checkpoint "${stem}_opt.dcp"}
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r -
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t {open_checkpoint "${stem}_rou.dcp"}
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}
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if {$lang eq "vhd"} {
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write_vhdl -mode funcsim -force "${stem}_${type}sim.vhd"
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} else {
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if {$type eq "s" || $type eq "o" || $type eq "r"} {
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write_verilog -mode funcsim -force "${stem}_${type}sim.v"
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} else {
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# use full absolute path name for sdf annotate
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# reason: the _tsim.v is sometimes generated in system path and
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# used from the tb path. xelab doesn't find the sdf in that case
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# Solution are absolute path (ugly) or symlink (ugly, who does setup..)
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write_verilog -mode timesim -force \
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-sdf_anno true \
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-sdf_file "[pwd]/${stem}_${type}sim.sdf" \
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"${stem}_${type}sim.v"
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write_sdf -mode timesim -force \
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-process_corner slow \
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"${stem}_${type}sim.sdf"
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}
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}
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} else {
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error "rvtb_default_model-E: bad mode: $mode";
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}
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return;
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}
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