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35 lines
1.2 KiB
Tcl
35 lines
1.2 KiB
Tcl
# -*- tcl -*-
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# $Id: cdc_vector_s0.xdc 830 2016-12-26 20:25:49Z mueller $
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#
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# Copyright 2016- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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# License disclaimer see License.txt in $RETROBASE directory
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#
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# cdc constraints for cdc_vector_s0
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#
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# Revision History:
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# Date Rev Version Comment
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# 2016-04-08 759 1.0 Initial version
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#
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# The following determines the input clock assuming that the synchronizer is
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# directly connected to a register. Will not work when logic is inbetween or
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# when driven by a dual-clocked BRAM.
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set clki [get_clocks -of_objects \
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[get_cells -of_objects \
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[get_pins -filter {DIRECTION==OUT && IS_LEAF==1} -of_objects \
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[get_nets -segments -of_objects \
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[get_ports -scoped_to_current_instance {DI[0]} ] ] ] ] ]
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set clki_per80 [expr {0.8 * [get_property -min PERIOD $clki]}]
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#
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# CLKI->CLK0
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# ensure delay and thus skew in DI smaller than a sender clock cycle
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# Note: the _s0 form should be used for 'quasi static' cases
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# this skew and delay control is therefore bit of an overkill
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set_max_delay \
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-from $clki \
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-to [get_cells {R_DO_S0_reg[*]}] \
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-datapath_only $clki_per80
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