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65 lines
1.9 KiB
VHDL
65 lines
1.9 KiB
VHDL
-- $Id: ib_sres_or_2.vhd 1181 2019-07-08 17:00:50Z mueller $
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-- SPDX-License-Identifier: GPL-3.0-or-later
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-- Copyright 2007-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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------------------------------------------------------------------------------
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-- Module Name: ib_sres_or_2 - syn
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-- Description: ibus: result or, 2 input
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--
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-- Dependencies: -
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-- Test bench: tb/tb_pdp11_core (implicit)
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-- Target Devices: generic
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-- Tool versions: ise 8.1-14.7; viv 2014.4; ghdl 0.18-0.31
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--
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-- Revision History:
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-- Date Rev Version Comment
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-- 2010-10-23 335 1.1 add ib_sres_or_mon
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-- 2008-08-22 161 1.0.2 renamed pdp11_ibres_ -> ib_sres_; use iblib
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-- 2008-01-05 110 1.0.1 rename IB_MREQ(ena->req) SRES(sel->ack, hold->busy)
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-- 2007-12-29 107 1.0 Initial version
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use work.slvtypes.all;
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use work.iblib.all;
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-- ----------------------------------------------------------------------------
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entity ib_sres_or_2 is -- ibus result or, 2 input
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port (
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IB_SRES_1 : in ib_sres_type; -- ib_sres input 1
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IB_SRES_2 : in ib_sres_type := ib_sres_init; -- ib_sres input 2
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IB_SRES_OR : out ib_sres_type -- ib_sres or'ed output
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);
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end ib_sres_or_2;
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architecture syn of ib_sres_or_2 is
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begin
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proc_comb : process (IB_SRES_1, IB_SRES_2)
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begin
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IB_SRES_OR.ack <= IB_SRES_1.ack or
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IB_SRES_2.ack;
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IB_SRES_OR.busy <= IB_SRES_1.busy or
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IB_SRES_2.busy;
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IB_SRES_OR.dout <= IB_SRES_1.dout or
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IB_SRES_2.dout;
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end process proc_comb;
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-- synthesis translate_off
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ORMON : ib_sres_or_mon
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port map (
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IB_SRES_1 => IB_SRES_1,
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IB_SRES_2 => IB_SRES_2,
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IB_SRES_3 => ib_sres_init,
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IB_SRES_4 => ib_sres_init
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);
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-- synthesis translate_on
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end syn;
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