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54 lines
1.5 KiB
VHDL
54 lines
1.5 KiB
VHDL
-- $Id: gen_crc8_tbl.vhd 1181 2019-07-08 17:00:50Z mueller $
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-- SPDX-License-Identifier: GPL-3.0-or-later
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-- Copyright 2007-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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------------------------------------------------------------------------------
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-- Module Name: gen_crc8_tbl - sim
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-- Description: stand-alone program to print crc8 transition table
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--
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-- Dependencies: comlib/crc8_update (function)
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--
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-- Revision History:
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-- Date Rev Version Comment
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-- 2011-09-17 410 1.1 now numeric_std clean; use function crc8_update
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-- 2007-10-12 88 1.0.1 avoid ieee.std_logic_unsigned, use cast to unsigned
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-- 2007-07-08 65 1.0 Initial version
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use std.textio.all;
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use work.slvtypes.all;
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use work.comlib.all;
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entity gen_crc8_tbl is
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end gen_crc8_tbl;
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architecture sim of gen_crc8_tbl is
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begin
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process
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variable crc : slv8 := (others=>'0');
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variable dat : slv8 := (others=>'0');
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variable nxt : slv8 := (others=>'0');
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variable oline : line;
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begin
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for i in 0 to 255 loop
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crc := (others=>'0');
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dat := slv(to_unsigned(i,8));
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nxt := crc8_update(crc, dat);
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write(oline, to_integer(unsigned(nxt)), right, 4);
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if i /= 255 then
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write(oline, string'(","));
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end if;
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if (i mod 8) = 7 then
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writeline(output, oline);
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end if;
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end loop; -- i
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wait;
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end process;
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end sim;
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