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104 lines
2.8 KiB
VHDL
104 lines
2.8 KiB
VHDL
-- $Id: rgbdrv_master.vhd 984 2018-01-02 20:56:27Z mueller $
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--
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-- Copyright 2016- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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-- This program is free software; you may redistribute and/or modify it under
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-- the terms of the GNU General Public License as published by the Free
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-- Software Foundation, either version 3, or (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful, but
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-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
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-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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-- for complete details.
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--
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------------------------------------------------------------------------------
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-- Module Name: rgbdrv_master - syn
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-- Description: rgbled driver: master
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--
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-- Dependencies: -
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-- Test bench: -
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-- Target Devices: generic
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-- Tool versions: viv 2015.4; ghdl 0.31
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--
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-- Revision History:
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-- Date Rev Version Comment
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-- 2016-02-20 734 1.0 Initial version
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.slvtypes.all;
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entity rgbdrv_master is -- rgbled driver: master
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generic (
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DWIDTH : positive := 8); -- dimmer width (must be >= 1)
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port (
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CLK : in slbit; -- clock
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RESET : in slbit := '0'; -- reset
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CE_USEC : in slbit; -- 1 us clock enable
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RGBCNTL : out slv3; -- rgb control
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DIMCNTL : out slv(DWIDTH-1 downto 0) -- dim control
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);
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end rgbdrv_master;
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architecture syn of rgbdrv_master is
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type regs_type is record
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rgbena : slv3; -- rgb enables
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dimcnt : slv(DWIDTH-1 downto 0); -- dim counter
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end record regs_type;
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constant dimones : slv(DWIDTH-1 downto 0) := (others=>'1');
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constant regs_init : regs_type := (
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"001", -- rgbena
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dimones -- dimcnt
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);
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signal R_REGS : regs_type := regs_init; -- state registers
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signal N_REGS : regs_type := regs_init; -- next value state regs
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begin
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proc_regs: process (CLK)
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begin
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if rising_edge(CLK) then
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if RESET = '1' then
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R_REGS <= regs_init;
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else
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R_REGS <= N_REGS;
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end if;
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end if;
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end process proc_regs;
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proc_next: process (R_REGS, CE_USEC)
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variable r : regs_type := regs_init;
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variable n : regs_type := regs_init;
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begin
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r := R_REGS;
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n := R_REGS;
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if CE_USEC = '1' then
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n.dimcnt := slv(unsigned(r.dimcnt) + 1);
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if r.dimcnt = dimones then
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n.rgbena(2) := r.rgbena(1);
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n.rgbena(1) := r.rgbena(0);
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n.rgbena(0) := r.rgbena(2);
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end if;
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end if;
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N_REGS <= n;
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end process proc_next;
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RGBCNTL <= R_REGS.rgbena;
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DIMCNTL <= R_REGS.dimcnt;
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end syn;
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