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https://github.com/wfjm/w11.git
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148 lines
5.3 KiB
Tcl
148 lines
5.3 KiB
Tcl
# $Id: defs.tcl 1044 2018-09-15 11:12:07Z mueller $
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#
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# Copyright 2014-2018 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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#
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# This program is free software; you may redistribute and/or modify it under
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# the terms of the GNU General Public License as published by the Free
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# Software Foundation, either version 3, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful, but
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# WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
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# or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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# for complete details.
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#
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# Revision History:
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# Date Rev Version Comment
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# 2018-09-09 1044 1.0.6 update defs kw11p, literals for KW11P_CSR(rate)
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# 2017-02-17 851 1.0.5 defs for auxilliary devices (kw11l,kw11p,iist)
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# 2016-12-30 834 1.0.4 fix typo in regmap_add for SDR's
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# 2016-01-02 724 1.0.3 add s: defs for CP_STAT(rust)
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# 2015-12-26 719 1.0.2 add regmap_add defs; add CNTRL def
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# 2015-09-06 710 1.0.1 regdsc PSW: add silent n,z,v,c; *mode syms; fix tflag
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# 2014-03-07 553 1.0 Initial version (extracted from util.tcl)
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#
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package provide rw11 1.0
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package require rlink
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package require rwxxtpp
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package require rw11util
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namespace eval rw11 {
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#
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# setup cp interface register descriptions for w11a -----------------------
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#
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regdsc CP_CNTL {func 3 0}
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regdsc CP_STAT {suspext 9} {suspint 8} \
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{rust 7 4 "s:init:halt:reset:stop:step:susp:hbpt:runs:vecfet:recrsv:s1010:s1011:sfail:vfail:s1110:s1111"} \
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{susp 3} {go 2} {merr 1} {err 0}
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variable RUST_INIT [bvi b4 "0000"]
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variable RUST_HALT [bvi b4 "0001"]
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variable RUST_RESET [bvi b4 "0010"]
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variable RUST_STOP [bvi b4 "0011"]
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variable RUST_STEP [bvi b4 "0100"]
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variable RUST_SUSP [bvi b4 "0101"]
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variable RUST_HBPT [bvi b4 "0110"]
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variable RUST_RUNS [bvi b4 "0111"]
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variable RUST_VECFET [bvi b4 "1000"]
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variable RUST_RECRSV [bvi b4 "1001"]
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variable RUST_SFAIL [bvi b4 "1100"]
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variable RUST_VFAIL [bvi b4 "1101"]
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regdsc CP_AH {ubm 7} {p22 6} {addr 5 6}
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#
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# setup w11a register descriptions -----------------------------------------
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#
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# PSW - processor status word --------------------------------------
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set A_PSW 0177776
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regdsc PSW {cmode 15 2 "s:k:s:x:u"} {pmode 13 2 "s:k:s:x:u"} \
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{rset 11} {pri 7 3 "d"} {tflag 4} {cc 3 4} \
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{n 3 1 "-"} {z 2 1 "-"} {v 1 1 "-"} {c 0 1 "-"}
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#
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# SSR0 - MMU Segment Status Register #0 ----------------------------
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set A_SSR0 0177572
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regdsc SSR0 {abo_nonres 15} {abo_len 14} {abo_rd 13} \
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{trap_mmu 12} {ena_trap 9} {inst_compl 7} \
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{mode 6 2} {dspace 4} {num 3 3} {ena 0}
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#
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# SSR1 - MMU Segment Status Register #1 ----------------------------
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set A_SSR1 0177574
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regdsc SSR1 {delta1 15 5} {rnum1 10 3} {delta0 7 5} {rnum0 2 3}
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#
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# SSR2 - MMU Segment Status Register #2 ----------------------------
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set A_SSR2 0177576
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#
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# SSR3 - MMU Segment Status Register #3 ----------------------------
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set A_SSR3 0172516
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regdsc SSR3 {ena_ubm 5} {ena_22bit 4} {d_km 2} {d_sm 1} {d_um 0}
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#
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# SAR/SDR - MMU Address/Segment Descriptor Register ----------------
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set A_SDR_KM 0172300
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set A_SAR_KM 0172340
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set A_SDR_SM 0172200
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set A_SAR_SM 0172240
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set A_SDR_UM 0177600
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set A_SAR_UM 0177640
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regdsc SDR {slf 14 7} {aia 7} {aiw 6} {ed 3} {acf 2 3}
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#
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# PIRQ - Program Interrupt Requests -------------------------------
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set A_PIRQ 0177772
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regdsc PIRQ {pir 15 7} {piah 7 3} {pial 3 3}
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#
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# CPUERR - CPU Error Register -------------------------------------
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set A_CPUERR 0177766
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regdsc CPUERR {illhlt 7} {adderr 6} {nxm 5} {iobto 4} {ysv 3} {rsv 2}
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#
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# CNTRL - Memory System Control Register -------------------------
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set A_CNTRL 0177746
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regdsc CNTRL {frep 5 2} {fmiss 3 2} {disutrap 1} {distrap 0}
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#
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# setup regmap
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#
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rw11util::regmap_add rw11 psw {?? PSW}
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rw11util::regmap_add rw11 ssr0 {?? SSR0}
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rw11util::regmap_add rw11 ssr1 {?? SSR1}
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rw11util::regmap_add rw11 ssr3 {?? SSR3}
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rw11util::regmap_add rw11 sdr??.? {?? SDR}
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rw11util::regmap_add rw11 pirq {?? PIRQ}
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rw11util::regmap_add rw11 cpuerr {?? CPUERR}
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#
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rw11util::regmap_add rw11 cntrl {?? CNTRL}
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#
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# other w11a definitions ---------------------------------------------------
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#
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# KW11-L line clock
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set A_KW11L_CSR 0177546
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regdsc KW11L_CSR {moni 7} {ie 6}
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rw11util::regmap_add rw11 kwl.csr {?? KW11L_CSR}
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#
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# KW11-P line clock
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set A_KW11P_CSR 0172540
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set A_KW11P_CSB 0172542
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set A_KW11P_CTR 0172544
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regdsc KW11P_CSR {err 15} {done 7} {ie 6} {fix 5} {updn 4} {mode 3} \
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{rate 2 2 "s:r100k:r10k:rline:rext"} {run 0}
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rw11util::regmap_add rw11 kwp.csr {?? KW11P_CSR}
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#
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# IIST - interprocessor communication
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set A_IIST_ACR 0177500
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set A_IIST_ADR 0177502
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regdsc IIST_ACR {clr 15} {sid 9 2} {ac 3 4}
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rw11util::regmap_add rw11 iist.acr {?? IIST_ACR}
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#
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# Interrupt vectors -----------------------------------------------
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#
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set V_004 0000004
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set V_010 0000010
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set V_BPT 0000014
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set V_IOT 0000020
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set V_PWR 0000024
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set V_EMT 0000030
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set V_TRAP 0000034
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set V_PIRQ 0000240
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set V_FPU 0000244
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set V_MMU 0000250
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}
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