mirror of
https://github.com/wfjm/w11.git
synced 2026-04-24 19:40:39 +00:00
44c96ec4ab
- rtl/w11a:
- pdp11.vhd: add cpustat_type treq_tbit and resetcnt; use op_rti rather op_rtt
- pdp11_decode.vhd: use op_rti rather op_rtt
- pdp11_sequencer.vhd: tbit logic overhaul; use treq_tbit; cleanups;
use resetcnt for 8 cycle RESET wait
- rtl/sys_gen/w11a/s3board/sys_conf.vhd: disable monitors for timing closure
- rtl/sys_gen/w11a/*/*.vmfset: drop removed signals
- tools
- asm-11/lib/push_pop.mac: add push2
- tbench/w11a/test_w11a_inst_quick.tcl: use creset option to clr pending traps
- tcl/rw11/asm.tcl: asmrun: add creset option (active with ps option)
- tcode/cpu_basics.mac: add F2.3 (reset settling time)
- tcode/cpu_details.mac: add A4.* (PSW + tbit traps)
This directory sub-tree contains w11a systems and is organized in
| Directory | Content |
|---|---|
| arty | design for Digilent Arty A7-35 (use DDR via MIG) |
| arty_bram | design for Digilent Arty A7-35 (use BRAM only) |
| artys7 | design for Digilent Arty S7-50 (use DDR via MIG) !! only sim-tested !! |
| artys7_bram | design for Digilent Arty S7-50 (use BRAM only) !! only sim-tested !! |
| basys3 | design for Digilent Basys3 |
| cmoda7 | design for Digilent Cmod A7-35 |
| nexys2 | design for Digilent Nexys2 |
| nexys3 | design for Digilent Nexys3 |
| nexys4 | design for Digilent Nexys4 (old CRAM version) |
| nexys4d | design for Digilent Nexys A7-100 (use DDR via MIG) |
| nexys4d_bram | design for Digilent Nexys A7-100 (use BRAM only |
| s3board | design for Digilent S3BOARD |