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139 lines
4.3 KiB
VHDL
139 lines
4.3 KiB
VHDL
-- $Id: ibdr_sdreg.vhd 1181 2019-07-08 17:00:50Z mueller $
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-- SPDX-License-Identifier: GPL-3.0-or-later
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-- Copyright 2007-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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------------------------------------------------------------------------------
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-- Module Name: ibdr_sdreg - syn
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-- Description: ibus dev(rem): Switch/Display register
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--
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-- Dependencies: -
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-- Test bench: -
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-- Target Devices: generic
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-- Tool versions: ise 8.2-14.7; viv 2014.4; ghdl 0.18-0.31
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--
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-- Synthesized (xst):
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-- Date Rev ise Target flop lutl lutm slic t peri
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-- 2010-10-17 333 12.1 M53d xc3s1000-4 34 40 0 30 s 4.0
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-- 2009-07-11 232 10.1.03 K39 xc3s1000-4 32 39 0 29 s 2.5
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--
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-- Revision History:
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-- Date Rev Version Comment
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-- 2011-11-18 427 1.2.1 now numeric_std clean
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-- 2010-10-17 333 1.2 use ibus V2 interface
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-- 2010-06-11 303 1.1 use IB_MREQ.racc instead of RRI_REQ
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-- 2008-08-22 161 1.0.4 use iblib
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-- 2008-04-18 136 1.0.3 use RESET. Switch/Display not cleared by console
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-- reset or reset instruction, only by cpu_reset
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-- 2008-01-20 112 1.0.2 use BRESET
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-- 2008-01-05 110 1.0.1 rename IB_MREQ(ena->req) SRES(sel->ack, hold->busy)
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-- reorganize code, all in state_type/proc_next
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-- 2007-12-31 108 1.0 Initial version
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.slvtypes.all;
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use work.iblib.all;
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-- ----------------------------------------------------------------------------
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entity ibdr_sdreg is -- ibus dev(rem): Switch/Display regs
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-- fixed address: 177570
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port (
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CLK : in slbit; -- clock
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RESET : in slbit; -- reset
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IB_MREQ : in ib_mreq_type; -- ibus request
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IB_SRES : out ib_sres_type; -- ibus response
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DISPREG : out slv16 -- display register
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);
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end ibdr_sdreg;
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architecture syn of ibdr_sdreg is
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constant ibaddr_sdreg : slv16 := slv(to_unsigned(8#177570#,16));
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type regs_type is record -- state registers
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ibsel : slbit; -- ibus select
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sreg : slv16; -- switch register
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dreg : slv16; -- display register
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end record regs_type;
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constant regs_init : regs_type := (
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'0', -- ibsel
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(others=>'0'), -- sreg
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(others=>'0') -- dreg
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);
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signal R_REGS : regs_type := regs_init;
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signal N_REGS : regs_type := regs_init;
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begin
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proc_regs: process (CLK)
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begin
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if rising_edge(CLK) then
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if RESET = '1' then
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R_REGS <= regs_init;
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else
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R_REGS <= N_REGS;
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end if;
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end if;
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end process proc_regs;
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proc_next : process (R_REGS, IB_MREQ)
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variable r : regs_type := regs_init;
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variable n : regs_type := regs_init;
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variable idout : slv16 := (others=>'0');
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variable ibreq : slbit := '0';
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begin
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r := R_REGS;
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n := R_REGS;
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idout := (others=>'0');
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ibreq := IB_MREQ.re or IB_MREQ.we;
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-- ibus address decoder
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n.ibsel := '0';
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if IB_MREQ.aval='1' and
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IB_MREQ.addr=ibaddr_sdreg(12 downto 1) then
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n.ibsel := '1';
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end if;
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-- ibus output driver
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if r.ibsel = '1' then
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if IB_MREQ.racc = '0' then
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idout := r.sreg; -- cpu will read switch register
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else
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idout := r.dreg; -- rri will read display register
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end if;
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end if;
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-- ibus write transactions
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if r.ibsel='1' and IB_MREQ.we='1' then
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if IB_MREQ.racc = '0' then -- cpu will write display register
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if IB_MREQ.be1 = '1' then
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n.dreg(ibf_byte1) := IB_MREQ.din(ibf_byte1);
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end if;
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if IB_MREQ.be0 = '1' then
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n.dreg(ibf_byte0) := IB_MREQ.din(ibf_byte0);
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end if;
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else -- rri will write switch register
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n.sreg := IB_MREQ.din; -- byte write not supported
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end if;
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end if;
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N_REGS <= n;
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IB_SRES.dout <= idout;
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IB_SRES.ack <= r.ibsel and ibreq;
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IB_SRES.busy <= '0';
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DISPREG <= r.dreg;
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end process proc_next;
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end syn;
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