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267 lines
6.6 KiB
Makefile
267 lines
6.6 KiB
Makefile
# $Id: generic_vivado.mk 1176 2019-06-30 07:16:06Z mueller $
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# SPDX-License-Identifier: GPL-3.0-or-later
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# Copyright 2015-2018 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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#
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# Revision History:
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# Date Rev Version Comment
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# 2018-12-22 1091 1.4.2 add bitgen flow checking
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# 2016-08-27 802 1.4.1 viv_clean: rm only vivado logs
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# 2016-07-22 792 1.4 relocate viv tcl code to tools/vivado
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# 2016-06-24 778 1.3 add rsim.vhd and [sorep]sim.v targets
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# 2016-06-11 774 1.2.1 call xviv_sim_vhdl_cleanup for %_[so]sim rules
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# 2016-05-27 769 1.2 add xviv_msg_filter support
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# 2016-03-26 752 1.1 new %.vivado; separate %_opt.dcp,%_pla.dcp,%_rou.dcp
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# 2015-02-15 646 1.0 Initial version
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# 2015-01-25 637 0.1 First draft
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#---
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#
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# check that part is defined
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#
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ifndef VIV_BOARD_SETUP
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$(error VIV_BOARD_SETUP is not defined)
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endif
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#
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# ensure that default tools and flows are defined
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#
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ifndef VIV_INIT
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VIV_INIT = ${RETROBASE}/tools/vivado/viv_init.tcl
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endif
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ifndef VIV_BUILD_FLOW
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VIV_BUILD_FLOW = ${RETROBASE}/tools/vivado/viv_default_build.tcl
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endif
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ifndef VIV_CONFIG_FLOW
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VIV_CONFIG_FLOW = ${RETROBASE}/tools/vivado/viv_default_config.tcl
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endif
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ifndef VIV_MODEL_FLOW
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VIV_MODEL_FLOW = ${RETROBASE}/tools/vivado/viv_default_model.tcl
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endif
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#
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# $@ first target
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# $< first dependency
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# $* stem in rule match
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#
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# when chaining, don't delete 'expensive' intermediate files:
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.SECONDARY :
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#
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# Setup vivado project
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# input: %.vbom vbom project description
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# output: .PHONY
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#
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%.vivado : %.vbom
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rm -rf project_mflow
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xtwv vivado -mode batch \
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-source ${VIV_INIT} \
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-source ${VIV_BOARD_SETUP} \
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-source ${VIV_BUILD_FLOW} \
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-tclargs $* prj
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#
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# Synthesize + Implement -> generate bit file
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# input: %.vbom vbom project description
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# output: %.bit
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#
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%.bit : %.vbom
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rm -rf project_mflow
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xtwv vivado -mode batch \
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-source ${VIV_INIT} \
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-source ${VIV_BOARD_SETUP} \
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-source ${VIV_BUILD_FLOW} \
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-tclargs $* bit
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@ if [ -r $*.vmfset ]; then make $*.mfsum; fi
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#
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# Print log file summary
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# input: %_*.log (not depended)
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# output: .PHONY
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%.mfsum: %.vmfset
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@ echo "=== Synthesis flow summary =================================="
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@ if [ -r $*_syn.log ]; \
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then xviv_msg_filter syn $*.vmfset $*_syn.log; \
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else echo " !!! no $*_syn.log found"; fi
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@ echo "=== Implementation flow summary ============================="
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@ if [ -r $*_imp.log ]; \
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then xviv_msg_filter imp $*.vmfset $*_imp.log; \
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else echo " !!! no $*_imp.log found"; fi
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@ echo "=== Bitgen flow summary ====================================="
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@ if [ -r $*_bit.log ]; \
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then xviv_msg_filter bit $*.vmfset $*_bit.log; \
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else echo " !!! no $*_bit.log found"; fi
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#
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# Configure FPGA with vivado hardware server
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# input: %.bit
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# output: .PHONY
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#
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%.vconfig : %.bit
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xtwv vivado -mode batch \
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-source ${VIV_INIT} \
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-source ${VIV_BOARD_SETUP} \
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-source ${VIV_CONFIG_FLOW} \
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-tclargs $*
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#
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# Partial Synthesize + Implement -> generate dcp for model generation
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#
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# run synthesis only
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%_syn.dcp : %.vbom
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rm -rf project_mflow
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xtwv vivado -mode batch \
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-source ${VIV_INIT} \
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-source ${VIV_BOARD_SETUP} \
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-source ${VIV_BUILD_FLOW} \
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-tclargs $* syn
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#
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# run synthesis + implementation up to step opt_design
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%_opt.dcp : %.vbom
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rm -rf project_mflow
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xtwv vivado -mode batch \
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-source ${VIV_INIT} \
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-source ${VIV_BOARD_SETUP} \
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-source ${VIV_BUILD_FLOW} \
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-tclargs $* opt
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#
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# run synthesis + implementation up to step place_design
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%_pla.dcp : %.vbom
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rm -rf project_mflow
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xtwv vivado -mode batch \
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-source ${VIV_INIT} \
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-source ${VIV_BOARD_SETUP} \
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-source ${VIV_BUILD_FLOW} \
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-tclargs $* pla
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#
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# run synthesis + implementation (but not bit file generation)
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%_rou.dcp : %.vbom
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rm -rf project_mflow
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xtwv vivado -mode batch \
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-source ${VIV_INIT} \
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-source ${VIV_BOARD_SETUP} \
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-source ${VIV_BUILD_FLOW} \
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-tclargs $* imp
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#
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# Post-synthesis functional simulation model (Vhdl/Unisim)
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# input: %_syn.dcp
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# output: %_ssim.vhd
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#
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%_ssim.vhd : %_syn.dcp
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xtwv vivado -mode batch \
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-source ${VIV_INIT} \
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-source ${VIV_MODEL_FLOW} \
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-tclargs $* ssim_vhd
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xviv_sim_vhdl_cleanup $@
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#
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# Post-optimization functional simulation model (Vhdl/Unisim)
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# input: %_opt.dcp
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# output: %_osim.vhd
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#
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%_osim.vhd : %_opt.dcp
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xtwv vivado -mode batch \
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-source ${VIV_INIT} \
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-source ${VIV_MODEL_FLOW} \
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-tclargs $* osim_vhd
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xviv_sim_vhdl_cleanup $@
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#
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# Post-routing functional simulation model (Vhdl/Unisim)
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# input: %_rou.dcp
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# output: %_rsim.vhd
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#
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%_rsim.vhd : %_rou.dcp
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xtwv vivado -mode batch \
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-source ${VIV_INIT} \
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-source ${VIV_MODEL_FLOW} \
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-tclargs $* rsim_vhd
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xviv_sim_vhdl_cleanup $@
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#
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# Post-synthesis functional simulation model (Verilog/Unisim)
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# input: %_syn.dcp
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# output: %_ssim.v
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#
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%_ssim.v : %_syn.dcp
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xtwv vivado -mode batch \
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-source ${VIV_INIT} \
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-source ${VIV_MODEL_FLOW} \
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-tclargs $* ssim_v
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#
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# Post-optimization functional simulation model (Verilog/Unisim)
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# input: %_opt.dcp
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# output: %_osim.v
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#
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%_osim.v : %_opt.dcp
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xtwv vivado -mode batch \
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-source ${VIV_INIT} \
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-source ${VIV_MODEL_FLOW} \
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-tclargs $* osim_v
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#
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# Post-routing functional simulation model (Verilog/Unisim)
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# input: %_rou.dcp
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# output: %_rsim.v
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#
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%_rsim.v : %_rou.dcp
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xtwv vivado -mode batch \
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-source ${VIV_INIT} \
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-source ${VIV_MODEL_FLOW} \
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-tclargs $* rsim_v
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#
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# Post-synthesis timing simulation model (Verilog/Simprim)
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# input: %_syn.dcp
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# output: %_esim.v
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# %_esim.sdf
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#
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%_esim.v %_esim.sdf : %_syn.dcp
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xtwv vivado -mode batch \
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-source ${VIV_INIT} \
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-source ${VIV_MODEL_FLOW} \
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-tclargs $* esim_v
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#
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# Post-optimization timing simulation model (Verilog/Simprim)
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# input: %_opt.dcp
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# output: %_psim.v
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# %_psim.sdf
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#
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%_psim.v %_psim.sdf : %_opt.dcp
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xtwv vivado -mode batch \
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-source ${VIV_INIT} \
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-source ${VIV_MODEL_FLOW} \
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-tclargs $* psim_v
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#
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# Post-routing timing simulation model (Verilog/Simprim)
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# input: %_rou.dcp
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# output: %_tsim.v
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# %_tsim.sdf
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#
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%_tsim.v %_tsim.sdf : %_rou.dcp
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xtwv vivado -mode batch \
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-source ${VIV_INIT} \
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-source ${VIV_MODEL_FLOW} \
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-tclargs $* tsim_v
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#
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# vivado project quick starter
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#
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.PHONY : vivado
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vivado :
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xtwv vivado -mode gui project_mflow/project_mflow.xpr
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#
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# generate dep_vsyn files from vbom
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#
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%.dep_vsyn: %.vbom
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vbomconv --dep_vsyn $< > $@
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#
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# Cleanup
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#
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include ${RETROBASE}/rtl/make_viv/dontincdep.mk
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#
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.PHONY : viv_clean viv_tmp_clean
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#
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viv_clean: viv_tmp_clean
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rm -f *.bit
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rm -f *.dcp
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rm -f *.jou
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rm -f *_bit.log
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rm -f *_imp.log
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rm -f *_syn.log
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rm -f *.rpt
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rm -f *_[sor]sim.vhd
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rm -f *_[sorept]sim.v
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rm -f *_[ept]sim.sdf
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#
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viv_tmp_clean:
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rm -rf ./project_mflow
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#
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