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131 lines
3.7 KiB
VHDL
131 lines
3.7 KiB
VHDL
-- $Id: pdp11_bram.vhd 1181 2019-07-08 17:00:50Z mueller $
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-- SPDX-License-Identifier: GPL-3.0-or-later
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-- Copyright 2008-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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------------------------------------------------------------------------------
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-- Module Name: pdp11_bram - syn
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-- Description: pdp11: BRAM based ext. memory dummy
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--
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-- Dependencies: memlib/ram_2swsr_rfirst_gen
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-- Test bench: -
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-- Target Devices: generic
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-- Tool versions: ise 8.2-14.7; viv 2014.4; ghdl 0.18-0.31
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-- Revision History:
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-- Date Rev Version Comment
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-- 2011-11-18 427 1.0.3 now numeric_std clean
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-- 2008-03-01 120 1.0.2 add addrzero constant to avoid XST errors
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-- 2008-02-23 118 1.0.1 AWIDTH now a generic port
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-- 2008-02-17 117 1.0 Initial version
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.slvtypes.all;
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use work.memlib.all;
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use work.pdp11.all;
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entity pdp11_bram is -- cache
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generic (
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AWIDTH : positive := 14); -- address width
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port (
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CLK : in slbit; -- clock
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GRESET : in slbit; -- general reset
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EM_MREQ : in em_mreq_type; -- em request
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EM_SRES : out em_sres_type -- em response
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);
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end pdp11_bram;
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architecture syn of pdp11_bram is
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type regs_type is record
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req_r : slbit; -- read request
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req_w : slbit; -- write request
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be : slv2; -- byte enables
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addr : slv(AWIDTH-1 downto 1); -- address
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end record regs_type;
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constant addrzero : slv(AWIDTH-1 downto 1) := (others=>'0');
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constant regs_init : regs_type := (
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'0','0', -- req_r,w
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(others=>'0'), -- be
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addrzero -- addr
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);
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signal R_REGS : regs_type := regs_init; -- state registers
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signal N_REGS : regs_type := regs_init; -- next value state regs
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signal MEM_ENB : slbit := '0';
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signal MEM_WEA : slv2 := "00";
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signal MEM_DOA : slv16 := (others=>'0');
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begin
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MEM_BYT0 : ram_2swsr_rfirst_gen
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generic map (
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AWIDTH => AWIDTH-1,
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DWIDTH => 8)
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port map (
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CLKA => CLK,
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CLKB => CLK,
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ENA => EM_MREQ.req,
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ENB => MEM_ENB,
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WEA => MEM_WEA(0),
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WEB => R_REGS.be(0),
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ADDRA => EM_MREQ.addr(AWIDTH-1 downto 1),
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ADDRB => R_REGS.addr,
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DIA => EM_MREQ.din(7 downto 0),
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DIB => MEM_DOA(7 downto 0),
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DOA => MEM_DOA(7 downto 0),
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DOB => open
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);
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MEM_BYT1 : ram_2swsr_rfirst_gen
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generic map (
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AWIDTH => AWIDTH-1,
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DWIDTH => 8)
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port map (
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CLKA => CLK,
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CLKB => CLK,
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ENA => EM_MREQ.req,
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ENB => MEM_ENB,
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WEA => MEM_WEA(1),
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WEB => R_REGS.be(1),
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ADDRA => EM_MREQ.addr(AWIDTH-1 downto 1),
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ADDRB => R_REGS.addr,
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DIA => EM_MREQ.din(15 downto 8),
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DIB => MEM_DOA(15 downto 8),
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DOA => MEM_DOA(15 downto 8),
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DOB => open
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);
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proc_regs: process (CLK)
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begin
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if rising_edge(CLK) then
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if GRESET = '1' then
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R_REGS <= regs_init;
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else
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R_REGS <= N_REGS;
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end if;
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end if;
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end process proc_regs;
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N_REGS.req_r <= EM_MREQ.req and not EM_MREQ.we;
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N_REGS.req_w <= EM_MREQ.req and EM_MREQ.we;
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N_REGS.be <= EM_MREQ.be;
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N_REGS.addr <= EM_MREQ.addr(N_REGS.addr'range);
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MEM_WEA(0) <= EM_MREQ.we and EM_MREQ.be(0);
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MEM_WEA(1) <= EM_MREQ.we and EM_MREQ.be(1);
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MEM_ENB <= EM_MREQ.cancel and R_REGS.req_w;
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EM_SRES.ack_r <= R_REGS.req_r;
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EM_SRES.ack_w <= R_REGS.req_w;
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EM_SRES.dout <= MEM_DOA;
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end syn;
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