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106 lines
3.5 KiB
VHDL
106 lines
3.5 KiB
VHDL
-- $Id: pdp11_ounit.vhd 1181 2019-07-08 17:00:50Z mueller $
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-- SPDX-License-Identifier: GPL-3.0-or-later
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-- Copyright 2006-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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------------------------------------------------------------------------------
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-- Module Name: pdp11_ounit - syn
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-- Description: pdp11: arithmetic unit for addresses (ounit)
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--
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-- Dependencies: -
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-- Test bench: tb/tb_pdp11_core (implicit)
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-- Target Devices: generic
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-- Tool versions: ise 8.2-14.7; viv 2014.4; ghdl 0.18-0.31
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-- Revision History:
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-- Date Rev Version Comment
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-- 2011-11-18 427 1.1.1 now numeric_std clean
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-- 2010-09-18 300 1.1 renamed from abox
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-- 2007-06-14 56 1.0.1 Use slvtypes.all
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-- 2007-05-12 26 1.0 Initial version
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.slvtypes.all;
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use work.pdp11.all;
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-- ----------------------------------------------------------------------------
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entity pdp11_ounit is -- offset adder for addresses (ounit)
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port (
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DSRC : in slv16; -- 'src' data for port A
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DDST : in slv16; -- 'dst' data for port A
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DTMP : in slv16; -- 'tmp' data for port A
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PC : in slv16; -- PC data for port A
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ASEL : in slv2; -- selector for port A
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AZERO : in slbit; -- force zero for port A
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IREG8 : in slv8; -- 'ireg' data for port B
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VMDOUT : in slv16; -- virt. memory data for port B
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CONST : in slv9; -- sequencer const data for port B
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BSEL : in slv2; -- selector for port B
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OPSUB : in slbit; -- operation: 0 add, 1 sub
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DOUT : out slv16; -- data output
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NZOUT : out slv2 -- NZ condition codes out
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);
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end pdp11_ounit;
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architecture syn of pdp11_ounit is
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-- --------------------------------------
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begin
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process (DSRC, DDST, DTMP, PC, ASEL, AZERO,
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IREG8, VMDOUT, CONST, BSEL, OPSUB)
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variable ma : slv16 := (others=>'0'); -- effective port a data
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variable mb : slv16 := (others=>'0'); -- effective port b data
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variable sum : slv16 := (others=>'0'); -- sum
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variable nzo : slbit := '0';
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begin
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if AZERO = '0' then
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case ASEL is
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when c_ounit_asel_dsrc => ma := DSRC;
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when c_ounit_asel_ddst => ma := DDST;
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when c_ounit_asel_dtmp => ma := DTMP;
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when c_ounit_asel_pc => ma := PC;
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when others => null;
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end case;
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else
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ma := (others=>'0');
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end if;
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case BSEL is
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when c_ounit_bsel_ireg6 => mb := "000000000" & IREG8(5 downto 0) & "0";
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when c_ounit_bsel_ireg8 => mb := IREG8(7) & IREG8(7) & IREG8(7) &
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IREG8(7) & IREG8(7) & IREG8(7) &
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IREG8(7) & IREG8 & "0";
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when c_ounit_bsel_vmdout => mb := VMDOUT;
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when c_ounit_bsel_const => mb := "0000000" & CONST;
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when others => null;
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end case;
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if OPSUB = '0' then
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sum := slv(unsigned(ma) + unsigned(mb));
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else
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sum := slv(unsigned(ma) - unsigned(mb));
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end if;
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nzo := '0';
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if unsigned(sum) = 0 then
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nzo := '1';
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else
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nzo := '0';
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end if;
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DOUT <= sum;
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NZOUT(1) <= sum(15);
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NZOUT(0) <= nzo;
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end process;
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end syn;
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