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32 lines
1.0 KiB
VHDL
32 lines
1.0 KiB
VHDL
-- $Id: pdp11_sim.vhd 1181 2019-07-08 17:00:50Z mueller $
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-- SPDX-License-Identifier: GPL-3.0-or-later
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-- Copyright 2006-2007 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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------------------------------------------------------------------------------
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-- Package Name: pdp11_sim
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-- Description: Definitions for simulations
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--
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-- Dependencies: -
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-- Tool versions: xst 8.1-14.7; ghdl 0.18-0.31
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-- Revision History:
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-- Date Rev Version Comment
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-- 2007-10-12 88 1.0.2 avoid ieee.std_logic_unsigned, use cast to unsigned
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-- 2007-06-14 56 1.0.1 Use slvtypes.all
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-- 2007-05-12 26 1.0 Initial version
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_textio.all;
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use std.textio.all;
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package pdp11_sim is
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constant clock_period : Delay_length := 20 ns;
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constant clock_offset : Delay_length := 200 ns;
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constant setup_time : Delay_length := 5 ns;
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constant c2out_time : Delay_length := 5 ns;
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end package pdp11_sim;
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