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0c395856d7
- add fifo_simple_dram: simple fifo with CE/WE interface, dram based - add test benches for fifo_simple_dram, fifo_2c_dram, and fifo_2c_dram2 - add simclkv: test bench clock generator with variable period
10 lines
157 B
Plaintext
10 lines
157 B
Plaintext
# libs
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../slvtypes.vhd
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memlib.vhd
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# components
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[sim]ram_1swar_gen.vbom
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[xst]ram_1swar_gen_unisim.vbom
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[vsyn]ram_1swar_gen.vbom
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# design
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fifo_simple_dram.vhd
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