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0c395856d7
- add fifo_simple_dram: simple fifo with CE/WE interface, dram based - add test benches for fifo_simple_dram, fifo_2c_dram, and fifo_2c_dram2 - add simclkv: test bench clock generator with variable period
80 lines
2.5 KiB
VHDL
80 lines
2.5 KiB
VHDL
-- $Id: simclkv.vhd 984 2018-01-02 20:56:27Z mueller $
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--
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-- Copyright 2007-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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-- This program is free software; you may redistribute and/or modify it under
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-- the terms of the GNU General Public License as published by the Free
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-- Software Foundation, either version 3, or (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful, but
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-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
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-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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-- for complete details.
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--
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------------------------------------------------------------------------------
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-- Module Name: simclkv - sim
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-- Description: Clock generator for test benches, variable period
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--
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-- Dependencies: -
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-- Test bench: -
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-- Target Devices: generic
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-- Tool versions: xst 8.2-14.7; viv 2016.2; ghdl 0.18-0.33
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-- Revision History:
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-- Date Rev Version Comment
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-- 2016-09-03 805 2.0.1 CLK_STOP,CLK_HOLD now optional ports
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-- 2011-12-23 444 2.0 remove CLK_CYCLE output port
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-- 2011-11-21 432 1.0.2 now numeric_std clean
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-- 2008-03-24 129 1.0.1 CLK_CYCLE now 31 bits
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-- 2007-12-27 106 1.0 Initial version
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.slvtypes.all;
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entity simclkv is -- test bench clock generator
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-- with variable period
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port (
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CLK : out slbit; -- clock
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CLK_PERIOD : in Delay_length; -- clock period
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CLK_HOLD : in slbit := '0'; -- if 1, hold clocks in 0 state
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CLK_STOP : in slbit := '0' -- clock stop trigger
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);
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end entity simclkv;
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architecture sim of simclkv is
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begin
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clk_proc: process
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variable half_period : Delay_length := 0 ns;
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begin
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CLK <= '0';
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clk_loop: loop
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if CLK_HOLD = '1' then
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wait until CLK_HOLD='0';
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end if;
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half_period := CLK_PERIOD/2;
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CLK <= '1';
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wait for half_period;
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CLK <= '0';
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wait for CLK_PERIOD-half_period;
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exit clk_loop when CLK_STOP = '1';
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end loop;
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CLK <= '1'; -- final clock cycle for clk_sim
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wait for CLK_PERIOD/2;
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CLK <= '0';
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wait for CLK_PERIOD-CLK_PERIOD/2;
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wait; -- endless wait, simulator will stop
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end process;
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end sim;
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