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05c7d937c7
- general board support - c7_sram_memctl: SRAM memory controller (incl tb) - is61wv5128bll: simple memory model (incl tb) - sn_humanio_emu_rbus: human IO emulator - 92-retro-usb-persistent.rules: add more board rules - associated changes - sn_humanio_rbus: add stat_rbf_emu (=0); single cycle btn pulses - rgbdrv_analog(_rbus): add ACTLOW generic to invert output polarity - ti_rri: adopt Digilent autodetect for CmodA7 - add systems - tst_rlink: rlink tested - tst_sram: SRAM tester - w11a: w11a system with 672 kB memory (512 SRAM + 160 BRAM)
15 lines
425 B
Tcl
15 lines
425 B
Tcl
# -*- tcl -*-
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# $Id: cmoda7_pclk.xdc 906 2017-06-04 21:59:13Z mueller $
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#
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# Copyright 2017- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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# License disclaimer see License.txt in $RETROBASE directory
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#
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# Primary clocks for Digilent CmodA7
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#
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# Revision History:
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# Date Rev Version Comment
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# 2017-06-04 906 1.0 Initial version
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#
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create_clock -name I_CLK12 -period 83.33 -waveform {0 41.66} [get_ports I_CLK12]
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