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97 lines
3.4 KiB
VHDL
97 lines
3.4 KiB
VHDL
-- $Id: gen_crc8_tbl_check.vhd 984 2018-01-02 20:56:27Z mueller $
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--
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-- Copyright 2007-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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-- This program is free software; you may redistribute and/or modify it under
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-- the terms of the GNU General Public License as published by the Free
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-- Software Foundation, either version 3, or (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful, but
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-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
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-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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-- for complete details.
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--
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------------------------------------------------------------------------------
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-- Module Name: gen_crc8_tbl - sim
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-- Description: stand-alone program to test crc8 transition table
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--
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-- Dependencies: -
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--
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-- Revision History:
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-- Date Rev Version Comment
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-- 2011-09-17 410 1.1 use now 'A6' polynomial of Koopman et al.
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-- 2007-10-12 88 1.0.1 avoid ieee.std_logic_unsigned, use cast to unsigned
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-- 2007-07-08 65 1.0 Initial version
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use std.textio.all;
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entity gen_crc8_tbl_check is
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end gen_crc8_tbl_check;
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architecture sim of gen_crc8_tbl_check is
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begin
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process
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type crc8_tbl_type is array (0 to 255) of integer;
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variable crc8_tbl : crc8_tbl_type := -- generated with gen_crc8_tbl
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( 0, 77, 154, 215, 121, 52, 227, 174,
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242, 191, 104, 37, 139, 198, 17, 92,
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169, 228, 51, 126, 208, 157, 74, 7,
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91, 22, 193, 140, 34, 111, 184, 245,
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31, 82, 133, 200, 102, 43, 252, 177,
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237, 160, 119, 58, 148, 217, 14, 67,
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182, 251, 44, 97, 207, 130, 85, 24,
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68, 9, 222, 147, 61, 112, 167, 234,
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62, 115, 164, 233, 71, 10, 221, 144,
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204, 129, 86, 27, 181, 248, 47, 98,
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151, 218, 13, 64, 238, 163, 116, 57,
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101, 40, 255, 178, 28, 81, 134, 203,
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33, 108, 187, 246, 88, 21, 194, 143,
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211, 158, 73, 4, 170, 231, 48, 125,
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136, 197, 18, 95, 241, 188, 107, 38,
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122, 55, 224, 173, 3, 78, 153, 212,
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124, 49, 230, 171, 5, 72, 159, 210,
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142, 195, 20, 89, 247, 186, 109, 32,
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213, 152, 79, 2, 172, 225, 54, 123,
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39, 106, 189, 240, 94, 19, 196, 137,
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99, 46, 249, 180, 26, 87, 128, 205,
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145, 220, 11, 70, 232, 165, 114, 63,
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202, 135, 80, 29, 179, 254, 41, 100,
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56, 117, 162, 239, 65, 12, 219, 150,
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66, 15, 216, 149, 59, 118, 161, 236,
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176, 253, 42, 103, 201, 132, 83, 30,
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235, 166, 113, 60, 146, 223, 8, 69,
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25, 84, 131, 206, 96, 45, 250, 183,
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93, 16, 199, 138, 36, 105, 190, 243,
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175, 226, 53, 120, 214, 155, 76, 1,
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244, 185, 110, 35, 141, 192, 23, 90,
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6, 75, 156, 209, 127, 50, 229, 168
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);
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variable crc : integer := 0;
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variable oline : line;
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begin
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loop_i: for i in 0 to 255 loop
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write(oline, i, right, 4);
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write(oline, string'(": cycle length = "));
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crc := i;
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loop_n: for n in 1 to 256 loop
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crc := crc8_tbl(crc);
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if crc = i then
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write(oline, n, right, 4);
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writeline(output, oline);
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exit loop_n;
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end if;
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end loop; -- n
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end loop; -- i
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wait;
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end process;
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end sim;
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