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182 lines
6.7 KiB
VHDL
182 lines
6.7 KiB
VHDL
-- $Id: serport_uart_autobaud.vhd 984 2018-01-02 20:56:27Z mueller $
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--
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-- Copyright 2007-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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-- This program is free software; you may redistribute and/or modify it under
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-- the terms of the GNU General Public License as published by the Free
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-- Software Foundation, either version 3, or (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful, but
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-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
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-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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-- for complete details.
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--
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------------------------------------------------------------------------------
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-- Module Name: serport_uart_autobaud - syn
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-- Description: serial port UART - autobauder
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--
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-- Dependencies: -
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-- Test bench: tb/tb_serport_autobaud
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-- Target Devices: generic
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-- Tool versions: ise 8.2-14.7; viv 2014.4-2016.2; ghdl 0.18-0.33
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-- Revision History:
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-- Date Rev Version Comment
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-- 2016-05-22 767 1.1.1 don't init N_REGS (vivado fix for fsm inference)
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-- 2015-02-01 641 1.1 add CLKDIV_F
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-- 2011-10-22 417 1.0.4 now numeric_std clean
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-- 2010-04-18 279 1.0.3 change ccnt start value to -3, better rounding
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-- 2007-10-14 89 1.0.2 all instantiation with CDINIT=0
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-- 2007-10-12 88 1.0.1 avoid ieee.std_logic_unsigned, use cast to unsigned
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-- 2007-06-30 62 1.0 Initial version
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------------------------------------------------------------------------------
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-- NOTE: for test bench usage a copy of all serport_* entities, with _tb
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-- !!!! appended to the name, has been created in the /tb sub folder.
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-- !!!! Ensure to update the copy when this file is changed !!
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.slvtypes.all;
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entity serport_uart_autobaud is -- serial port uart: autobauder
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generic (
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CDWIDTH : positive := 13; -- clk divider width
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CDINIT: natural := 15); -- clk divider initial/reset setting
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port (
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CLK : in slbit; -- clock
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CE_MSEC : in slbit; -- 1 msec clock enable
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RESET : in slbit; -- reset
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RXSD : in slbit; -- receive serial data (uart view)
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CLKDIV : out slv(CDWIDTH-1 downto 0); -- clock divider setting
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CLKDIV_F: out slv3; -- clock divider fractional part
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ACT : out slbit; -- active; if 1 clkdiv is invalid
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DONE : out slbit -- resync done
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);
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end serport_uart_autobaud;
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architecture syn of serport_uart_autobaud is
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type state_type is (
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s_idle,
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s_break,
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s_wait,
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s_sync
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);
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type regs_type is record
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ccnt : slv(CDWIDTH-1+3 downto 0); -- clock divider counter
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mcnt : slv7; -- msec counter
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seen1 : slbit; -- seen a '1' in this msec
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state : state_type; -- state
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end record regs_type;
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-- Note on initialization of ccnt:
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-- - in the current logic ccnt is incremented n-1 times when n is number
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-- clock cycles with a RXD of '0'. When running at 50 MBaud, ccnt will
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-- be incremented 7 (not 8!) times.
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-- - the three LSBs of ccnt should be at 100 under perfect conditions, this
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-- gives the best rounded estimate of CLKDIV.
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-- - therefore ccnt is inititialized with 111111.101: 101 + 111 -> 1100
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-- --> ccntinit = -3
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constant ccntinit : slv(CDWIDTH-1+3 downto 0) :=
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slv(to_unsigned(2**(CDWIDTH+3)-3, CDWIDTH+3));
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constant mcntzero : slv7 := (others=>'0');
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constant mcntlast : slv7 := (others=>'1');
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constant regs_init : regs_type := (
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slv(to_unsigned(CDINIT,CDWIDTH))&"000",
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(others=>'0'),
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'0',
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s_idle
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);
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signal R_REGS : regs_type := regs_init;
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signal N_REGS : regs_type; -- don't init (vivado fix for fsm infer)
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begin
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assert CDINIT <= 2**CDWIDTH-1
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report "assert(CDINIT <= 2**CDWIDTH-1): CDINIT too large for given CDWIDTH"
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severity failure;
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proc_regs: process (CLK)
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begin
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if rising_edge(CLK) then
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if RESET = '1' then
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R_REGS <= regs_init;
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else
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R_REGS <= N_REGS;
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end if;
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end if;
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end process proc_regs;
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proc_next: process (R_REGS, CE_MSEC, RESET, RXSD)
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variable r : regs_type := regs_init;
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variable n : regs_type := regs_init;
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variable iact : slbit := '0';
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variable idone : slbit := '0';
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begin
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r := R_REGS;
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n := R_REGS;
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iact := '1';
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idone := '0';
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case r.state is
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when s_idle => -- s_idle: idle, detect break --------
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iact := '0';
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if CE_MSEC = '1' then -- if end of msec
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if r.seen1 = '0' then -- if no '1' seen on RXD
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n.mcnt := slv(unsigned(r.mcnt) + 1); -- up break timer counter
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if r.mcnt = mcntlast then -- after 127 msec
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n.state := s_break; -- break detected !
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end if;
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else -- otherwise if '1' seen
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n.mcnt := mcntzero; -- clear break timer again
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end if;
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n.seen1 := RXSD; -- latch current RXD value
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else -- otherwise if not at end-of-msec
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n.seen1 := r.seen1 or RXSD; -- remember whether RXS=1 seen
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end if;
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when s_break => -- s_break: detect end of break ------
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if RXSD = '1' then -- if end of break seen
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n.state := s_wait; -- to s_wait to wait for sync char
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n.ccnt := ccntinit; -- and initialize ccnt
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end if; -- otherwise stay in s_break
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when s_wait => -- s_wait: wait for sync char --------
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if RXSD = '0' then -- if start bit if sync char seen
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n.state := s_sync; -- to s_sync to wait for end of '0'
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end if; -- otherwise stay in s_wait
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when s_sync => -- s_sync: wait for end of '0' bits --
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if RXSD = '1' then -- if end of '0' bits seen
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n.state := s_idle; -- to s_idle, autobauding done
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idone := '1'; -- emit done pulse
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else -- otherwise still in '0' of sync
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n.ccnt := slv(unsigned(n.ccnt) + 1); -- increment ccnt
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end if;
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when others => null; -- -----------------------------------
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end case;
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N_REGS <= n;
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CLKDIV <= r.ccnt(CDWIDTH-1+3 downto 3);
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CLKDIV_F <= r.ccnt(2 downto 0);
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ACT <= iact or RESET;
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DONE <= idone;
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end process proc_next;
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end syn;
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